Inventor
BAJIC LJUBISA
CA37 patents
⚠️ This page may combine multiple inventors who share the name “BAJIC LJUBISA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TENSTORRENT INC
26 patentsUS11829752B2Nov 28, 2023
Processor cores using packet identifiers for routing and computation
TENSTORRENT INC3 citations71
US11010132B2May 18, 2021
Processing core with data associative adaptive rounding
TENSTORRENT INC1 citations70
US10644721B2May 5, 2020
Processing core data compression and storage system
TENSTORRENT INC2 citations70
US10318317B2Jun 11, 2019
Processing core with operation suppression based on contribution estimate
TENSTORRENT INC3 citations70
US12236237B2Feb 25, 2025
Processor cores using content object identifiers for routing and computation
TENSTORRENT INC0 citations61
US12118060B2Oct 15, 2024
Computational circuit with hierarchical accumulator
TENSTORRENT INC0 citations61
US11269628B2Mar 8, 2022
Processor cores using packet identifiers for routing and computation
TENSTORRENT INC0 citations61
US12050913B2Jul 30, 2024
Processing core with meta data actuated conditional graph execution
TENSTORRENT INC0 citations60
US12039289B2Jul 16, 2024
Processing core with data associative adaptive rounding
TENSTORRENT INC0 citations60
US12019546B2Jun 25, 2024
Data structure optimized dedicated memory caches
TENSTORRENT INC0 citations60
US11645041B2May 9, 2023
Processing core with data associative adaptive rounding
TENSTORRENT INC0 citations60
US11520701B2Dec 6, 2022
Data structure optimized dedicated memory caches
TENSTORRENT INC0 citations60
US11245643B2Feb 8, 2022
Speculative resource allocation for routing on interconnect fabrics
TENSTORRENT INC0 citations60
US10938413B2Mar 2, 2021
Processing core data compression and storage system
TENSTORRENT INC0 citations60
US10817293B2Oct 27, 2020
Processing core with metadata actuated conditional graph execution
TENSTORRENT INC1 citations60
US11960885B2Apr 16, 2024
Seamless place and route for heterogenous network of processor cores
TENSTORRENT INC0 citations59
US11301264B2Apr 12, 2022
Processing core with operation suppression based on contribution estimate
TENSTORRENT INC0 citations59
US11709662B2Jul 25, 2023
Sparsity uniformity enforcement for multicore processor
TENSTORRENT INC0 citations58
US11693639B2Jul 4, 2023
Sparsity uniformity enforcement for multicore processor
TENSTORRENT INC0 citations58
US12248430B2Mar 11, 2025
Overlay layer for network of processor cores
TENSTORRENT INC0 citations57
US12210478B2Jan 28, 2025
Overlay layer hardware unit for network of processor cores
TENSTORRENT INC0 citations57
US11734224B2Aug 22, 2023
Overlay layer hardware unit for network of processor cores
TENSTORRENT INC0 citations57
US11113051B2Sep 7, 2021
Processing core with metadata actuated conditional graph execution
TENSTORRENT INC1 citations56
US10585679B2Mar 10, 2020
Processing core with operation suppression based on contribution estimate
TENSTORRENT INC0 citations49
US11467846B2Oct 11, 2022
Overlay layer for network of processor cores
TENSTORRENT INC0 citations46
US11934897B2Mar 19, 2024
Application data flow graph execution using network-on-chip overlay
TENSTORRENT INC0 citations44
TENSTORRENT AI ULC
5 patentsUS12399713B2Aug 26, 2025
Multiplication hardware block with adaptive fidelity control system
TENSTORRENT AI ULC1 citations59
US12367041B2Jul 22, 2025
Seamless place and route for heterogeneous network of processor cores
TENSTORRENT AI ULC0 citations58
US12340185B2Jun 24, 2025
Processing core with data associative adaptive rounding
TENSTORRENT AI ULC0 citations58
US12260197B2Mar 25, 2025
Sparsity uniformity enforcement for multicore processor
TENSTORRENT AI ULC0 citations56
US12321855B2Jun 3, 2025
Graph execution using access request response dynamic batch assembly
TENSTORRENT AI ULC0 citations48