Inventor
CHEN JIUN-RUEY
US5 patents
Patents
5 patentsUS11444024B2Sep 13, 2022
Subtractively patterned interconnect structures for integrated circuits
INTEL CORP10 citations84
US12027458B2Jul 2, 2024
Subtractively patterned interconnect structures for integrated circuits
INTEL CORP2 citations71
US12482744B2Nov 25, 2025
Subtractively patterned interconnect structures for integrated circuits
INTEL CORP0 citations61
US12500162B2Dec 16, 2025
Staggered vertically spaced integrated circuit line metallization with differential vias and metal-selective deposition
INTEL CORP0 citations50
US12598977B2Apr 7, 2026
Fill of vias in single and dual damascene structures using self-assembled monolayer
INTEL CORP0 citations49