Inventor

MEYER PAUL GILBERT

US36 patents

⚠️ This page may combine multiple inventors who share the name “MEYER PAUL GILBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MEYER PAUL GILBERT

AMAZON TECH INC

Fine-grained sparsity computations in systolic array

Using shared data bus to support systolic array tiling

Matrix transpose hardware acceleration

Emulating fine-grained sparsity in a systolic array

Flexible array data loading

Programmable vector engine for efficient beam search

Systolic array with efficient input reduction and extended array performance

Fine-grained sparsity computations in systolic array

Resizable scratchpad memory

Programmable compute engine having transpose operations

Throughput increase for compute engine

Machine instructions for decoding acceleration including fuse input instructions to fuse multiple JPEG data blocks together to take advantage of a full SIMD width of a processor

Vector engine for efficient beam search

Configurable vector compute engine

Systolic array with input reduction to multiple reduced inputs

Reducing power consumption in integrated circuits

Matrix transpose hardware acceleration

Emulating fine-grained sparsity in a systolic array

Configuration of a deep vector engine using an opcode table, control table, and datapath table

Increasing performance of computational array accelerators

Throughput increase for tensor operations

Tile assignment for matrix multiplication packing

ADVANCED RISC MACH LTD

Inter-chip communication in a multi-chip system

Access control

Error detection circuitry for use with memory

Apparatus and method for processing an ownership upgrade request for cached data that is issued in relation to a conditional store operation

Memory controller having data access hint message for specifying the given range of one or more memory addresses

Cache content management

Memory controller having data access hint message for specifying the given range of one or more memory addresses

System address map for hashing within a chip and between chips

Data processing

Cache maintenance operations in a data processing system

Segregated power state control in a distributed cache system

Optimized streaming in an un-ordered interconnect

MCDONALD ROBERT GREGORY

Apparatus and method for early issue and recovery for a conditional load instruction having multiple outcomes

MEYER PAUL GILBERT

Method and apparatus with data storage protocols for maintaining consistencies in parallel translation lookaside buffers