Inventor

HUANG RANDY RENFU

US62 patents

⚠️ This page may combine multiple inventors who share the name “HUANG RANDY RENFU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUANG RANDY RENFU

AMAZON TECH INC

Fine-grained sparsity computations in systolic array

Allocation and placement of resources for network computation

Debug for computation networks using error detection codes

Secure data processing

Registers for restricted memory

Hardware implementation of mathematical functions

Static memory allocation for neural network inference

Neural network processing based on subgraph recognition

Power reduction in processor pipeline by detecting zeros

Multicast master

Global modulo allocation in neural network compilation

Emulating fine-grained sparsity in a systolic array

Low latency neural network model loading

Performing hardware operator fusion

Loop-oriented neural network compilation

Target port with distributed transactions

Workload reduction for non-maximum suppression operation

Data selection circuit

Dynamic processing element array expansion

Neural network training in a distributed system

Acceleration of neural networks with stacks of convolutional layers

Efficient utilization of processing element array

Dropout layer in a neural network processor

Dynamic processing element array expansion

Compilation time reduction for memory and compute bound neural networks

Top value computation on an integrated circuit device

Neural network operation reordering for parallel execution

Bidirectional network on a data-flow centric processor

Fine-grained sparsity computations in systolic array

Hardware implementation of mathematical functions

Target port with distributed transactions

Neural network processing based on subgraph recognition

Global modulo allocation in neural network compilation

Efficient utilization of processing element array

Emulating fine-grained sparsity in a systolic array

Neural network training under memory restraint

Neural network processing based on subgraph recognition

Compilation time reduction for memory and compute bound neural networks

Neural network training under memory restraint

Neural network operation reordering for parallel execution

TABULA INC

Configurable IC with routing circuits with offset connections

Configurable IC with routing circuits with offset connections

Configurable IC having a routing fabric with storage elements

Configurable IC&#39;s with configurable logic resources that have asymetric inputs and/or outputs

Configurable IC with configurable routing resources that have asymmetric input and/or outputs

Configurable IC with configuration logic resources that have asymmetric inputs and/or outputs

Configurable IC&#39;s with logic resources with offset connections

Configurable IC with logic resources with offset connections

TEIG STEVEN

Configurable IC having a routing fabric with storage elements

Configurable IC having a routing fabric with storage elements

Configurable IC's with configurable logic resources that have asymetric inputs and/or outputs

Configurable IC's with logic resources with offset connections