Inventor
FOUNTAIN JR GAIUS GILLMAN
US94 patents
⚠️ This page may combine multiple inventors who share the name “FOUNTAIN JR GAIUS GILLMAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INVENSAS BONDING TECH INC
18 patentsUS11011494B2May 18, 2021
Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
INVENSAS BONDING TECH INC133 citations99
US10879212B2Dec 29, 2020
Processed stacked dies
INVENSAS BONDING TECH INC155 citations99
US10446532B2Oct 15, 2019
Systems and methods for efficient transfer of semiconductor elements
INVENSAS BONDING TECH INC161 citations99
US9852988B2Dec 26, 2017
Increased contact alignment tolerance for direct bonding
INVENSAS BONDING TECH INC218 citations99
US11393779B2Jul 19, 2022
Large metal pads over TSV
INVENSAS BONDING TECH INC58 citations98
US11355404B2Jun 7, 2022
Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
INVENSAS BONDING TECH INC50 citations98
US11296044B2Apr 5, 2022
Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes
INVENSAS BONDING TECH INC80 citations98
US11158573B2Oct 26, 2021
Interconnect structures
INVENSAS BONDING TECH INC67 citations98
US11037919B2Jun 15, 2021
Techniques for processing devices
INVENSAS BONDING TECH INC88 citations98
US11004757B2May 11, 2021
Bonded structures
INVENSAS BONDING TECH INC117 citations98
US10964664B2Mar 30, 2021
DBI to Si bonding for simplified handle wafer
INVENSAS BONDING TECH INC153 citations98
US10840205B2Nov 17, 2020
Chemical mechanical polishing for hybrid bonding
INVENSAS BONDING TECH INC146 citations98
US10727219B2Jul 28, 2020
Techniques for processing devices
INVENSAS BONDING TECH INC90 citations98
US10269708B2Apr 23, 2019
Increased contact alignment tolerance for direct bonding
INVENSAS BONDING TECH INC49 citations98
US10147641B2Dec 4, 2018
3D IC method and device
INVENSAS BONDING TECH INC47 citations98
US11296053B2Apr 5, 2022
Direct bonded stack structures for increased reliability and improved yield in microelectronics
INVENSAS BONDING TECH INC41 citations97
US11011418B2May 18, 2021
3D IC method and device
INVENSAS BONDING TECH INC5 citations84
US10366962B2Jul 30, 2019
Three dimensional device integration method and integrated device
INVENSAS BONDING TECH INC5 citations84
ZIPTRONIX INC
18 patentsUS9431368B2Aug 30, 2016
Three dimensional device integration method and integrated device
ZIPTRONIX INC194 citations99
US9391143B2Jul 12, 2016
Method for low temperature bonding and bonded structure
ZIPTRONIX INC117 citations99
US9331149B2May 3, 2016
Method for low temperature bonding and bonded structure
ZIPTRONIX INC185 citations99
US9171756B2Oct 27, 2015
3D IC method and device
ZIPTRONIX INC232 citations99
US7485968B2Feb 3, 2009
3D IC method and device
ZIPTRONIX INC433 citations99
US7387944B2Jun 17, 2008
Method for low temperature bonding and bonded structure
ZIPTRONIX INC68 citations99
US7041178B2May 9, 2006
Method for low temperature bonding and bonded structure
ZIPTRONIX INC129 citations99
US6902987B1Jun 7, 2005
Method for low temperature bonding and bonded structure
ZIPTRONIX INC227 citations99
US9716033B2Jul 25, 2017
3D IC method and device
ZIPTRONIX INC29 citations98
US9564414B2Feb 7, 2017
Three dimensional device integration method and integrated device
ZIPTRONIX INC37 citations98
US9082627B2Jul 14, 2015
Method for low temperature bonding and bonded structure
ZIPTRONIX INC20 citations96
US7807549B2Oct 5, 2010
Method for low temperature bonding and bonded structure
ZIPTRONIX INC41 citations96
US7553744B2Jun 30, 2009
Method for low temperature bonding and bonded structure
ZIPTRONIX INC35 citations96
US7335572B2Feb 26, 2008
Method for low temperature bonding and bonded structure
ZIPTRONIX INC39 citations96
US8709938B2Apr 29, 2014
3D IC method and device
ZIPTRONIX INC13 citations93
US8053329B2Nov 8, 2011
Method for low temperature bonding and bonded structure
ZIPTRONIX INC7 citations93
US7871898B2Jan 18, 2011
Method for low temperature bonding and bonded structure
ZIPTRONIX INC9 citations93
US7462552B2Dec 9, 2008
Method of detachable direct bonding at low temperatures
ZIPTRONIX INC42 citations93
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC
10 patentsUS11652083B2May 16, 2023
Processed stacked dies
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC18 citations95
US12199069B2Jan 14, 2025
Heterogeneous annealing method and device
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC3 citations86
US11955445B2Apr 9, 2024
Metal pads over TSV
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC5 citations86
US11855064B2Dec 26, 2023
Techniques for processing devices
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC5 citations86
US11756880B2Sep 12, 2023
Interconnect structures
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC6 citations86
US11749645B2Sep 5, 2023
TSV as pad
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC8 citations86
US11955463B2Apr 9, 2024
Direct bonded stack structures for increased reliability and improved yield in microelectronics
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC6 citations85
US11791307B2Oct 17, 2023
DBI to SI bonding for simplified handle wafer
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC4 citations85
US11664357B2May 30, 2023
Techniques for joining dissimilar materials in microelectronics
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC15 citations85
US11552041B2Jan 10, 2023
Chemical mechanical polishing for hybrid bonding
ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC8 citations85
ZIPTRONIX
2 patentsTONG QIN-YI
1 patentENQUIST PAUL M
1 patentShowing the top 50 of 94 patents by PatentIndex Score.