Inventor
WASHBURN STEVEN EUGENE
US2 patents
Patents
2 patentsUS6571374B1May 27, 2003
Invention to allow multiple layouts for a schematic in hierarchical logical-to-physical checking on chips
IBM11 citations68
US10254784B1Apr 9, 2019
Using required arrival time constraints for coupled noise analysis and noise aware timing analysis of out-of-context (OOC) hierarchical entities
IBM1 citations55