Inventor

SATO NORIYUKI

US171 patents

⚠️ This page may combine multiple inventors who share the name “SATO NORIYUKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SATO NORIYUKI

KEPLER COMPUTING INC

Stacked ferroelectric non-planar capacitors in a memory bit-cell

Common mode compensation for non-linear polar material based 1T1C memory bit-cell

Non-linear polar material based memory bit-cell with multi-level storage by applying different voltage levels

High-density low voltage multi-element ferroelectric gain memory bit-cell with pillar capacitors

Stacked ferroelectric planar capacitors in a memory bit-cell

Method of forming stacked ferroelectric non- planar capacitors in a memory bit-cell

Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures and methods of fabrication

High-density low voltage multi-element ferroelectric gain memory bit-cell with planar capacitors

Memory devices with dual encapsulation layers and methods of fabrication

Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors with lateral offset

Stack of planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell

High-density low voltage ferroelectric memory bit-cell

Method of fabricating transistors and stacked planar capacitors for memory and logic applications

Memory device fabrication through wafer bonding

Multi-input threshold gate having stacked and folded non-planar capacitors

Memory bit-cell with stacked and folded planar capacitors

One transistor and N memory element based memory bit-cell having stacked and folded planar memory elements with and without offset

Multi-input threshold gate having stacked and folded planar capacitors with and without offset

1TnC memory bit-cell having stacked and folded non-planar capacitors

1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

Planar capacitors with non-linear polar material staggered on a shared electrode

Multi-element gain memory bit-cell having stacked and folded planar memory elements with and without offset

Pedestal-based pocket integration process for embedded memory

Multi-element ferroelectric gain memory bit-cell having stacked and folded non-planar capacitors

Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors

Multi-level hydrogen barrier layers for memory applications

Integrated via and bridge electrodes for memory array applications and methods of fabrication

Method of forming a stack of planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell

Process integration flow for embedded memory enabled by decoupling processing of a memory area from a non-memory area

Iterative monetization of process development of non-linear polar material and devices

Common mode compensation for non-linear polar material based differential memory bit-cell

Common mode compensation for multi-element non-linear polar material based gain memory bit-cell

Non-linear polar material based memory bit-cell with multi-level storage by applying different time pulse widths

INTEL CORP

Subtractively patterned interconnect structures for integrated circuits

Transistors, memory cells, and arrangements thereof

Spin orbit memory devices with reduced magnetic moment and methods of fabrication

Perpendicular exchange bias with antiferromagnet for spin orbit coupling based memory

Perpendicular spin transfer torque memory (pSTTM) devices with enhanced thermal stability and methods to form the same

Magnetically doped spin orbit torque electrode for perpendicular magnetic random access memory

Multi-level magnetic tunnel junction (MTJ) devices including mobile magnetic skyrmions or ferromagnetic domains

Multi-layer spin orbit torque electrodes for perpendicular magnetic random access memory

High blocking temperature spin orbit torque electrode

Self-aligned spin orbit torque (SOT) memory devices and their methods of fabrication

OKI ELECTRIC IND CO LTD

Decoding apparatus, coding apparatus, and transmission system employing two intra-frame error concealment methods

Transmission header compressor not compressing transmission headers attached to intra-frame coded moving-picture data

NIPPON TELEGRAPH & TELEPHONE

Communication facilities power supply control device, power supply control method, power supply control program, and power supply control system

Line verification device, and line verification method

YUTAKA GIKEN CO LTD

Method of connecting two elongated portions of metallic plate, method of manufacturing exhaust pipe of two-passage construction, and exhaust pipe of two-passage construction

TOYO SUISAN KAISHA

Sulfoquinovosylacylglycerol derivative, and use thereof as medicaments

SEIKO EPSON CORP

Projector having an adjuster to adjust an angle of a projector lens