Inventor

OLAOSEBIKAN DEBO

US54 patents

Patents

50 patents

US11694940B1Jul 4, 2023

Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging

KEPLER COMPUTING INC8 citations94

US11545204B1Jan 3, 2023

Non-linear polar material based memory bit-cell with multi-level storage by applying different voltage levels

KEPLER COMPUTING INC10 citations94

US11532635B1Dec 20, 2022

High-density low voltage multi-element ferroelectric gain memory bit-cell with pillar capacitors

KEPLER COMPUTING INC10 citations94

US11521667B1Dec 6, 2022

Stacked ferroelectric planar capacitors in a memory bit-cell

KEPLER COMPUTING INC11 citations94

US11501813B1Nov 15, 2022

Method of forming stacked ferroelectric non- planar capacitors in a memory bit-cell

KEPLER COMPUTING INC11 citations94

US12243797B1Mar 4, 2025

3D stack of split graphics processing logic dies

KEPLER COMPUTING INC5 citations86

US12086410B1Sep 10, 2024

Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer

KEPLER COMPUTING INC7 citations86

US12079475B1Sep 3, 2024

Ferroelectric memory chiplet in a multi-dimensional packaging

KEPLER COMPUTING INC13 citations86

US12026034B1Jul 2, 2024

Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic

KEPLER COMPUTING INC3 citations86

US12019492B1Jun 25, 2024

Method and apparatus for managing power in a multi-dimensional packaging

KEPLER COMPUTING INC3 citations86

US12001266B1Jun 4, 2024

Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic

KEPLER COMPUTING INC3 citations86

US11899613B1Feb 13, 2024

Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging

KEPLER COMPUTING INC6 citations86

US11844223B1Dec 12, 2023

Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging

KEPLER COMPUTING INC8 citations86

US11829699B1Nov 28, 2023

Method to segregate logic and memory into separate dies for thermal management in a multi-dimensional packaging

KEPLER COMPUTING INC5 citations86

US11664371B1May 30, 2023

Multi-function threshold gate with adaptive threshold and stacked planar paraelectric capacitors

KEPLER COMPUTING INC7 citations86

US11521666B1Dec 6, 2022

High-density low voltage multi-element ferroelectric gain memory bit-cell with planar capacitors

KEPLER COMPUTING INC6 citations86

US11841757B1Dec 12, 2023

Method and apparatus for cycle-by-cycle clock gating of ferroelectric or paraelectric logic and CMOS based logic

KEPLER COMPUTING INC3 citations84

US11837268B1Dec 5, 2023

Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors with lateral offset

KEPLER COMPUTING INC3 citations84

US11527277B1Dec 13, 2022

High-density low voltage ferroelectric memory bit-cell

KEPLER COMPUTING INC3 citations84

US12171103B1Dec 17, 2024

Multi-input threshold gate having stacked and folded non-planar capacitors

KEPLER COMPUTING INC1 citations73

US12166011B1Dec 10, 2024

Method of forming an artificial intelligence processor with three-dimensional stacked memory

KEPLER COMPUTING INC2 citations73

US12108609B1Oct 1, 2024

Memory bit-cell with stacked and folded planar capacitors

KEPLER COMPUTING INC1 citations73

US12096638B2Sep 17, 2024

One transistor and N memory element based memory bit-cell having stacked and folded planar memory elements with and without offset

KEPLER COMPUTING INC1 citations73

US12087730B1Sep 10, 2024

Multi-input threshold gate having stacked and folded planar capacitors with and without offset

KEPLER COMPUTING INC1 citations73

US12041785B1Jul 16, 2024

1TnC memory bit-cell having stacked and folded non-planar capacitors

KEPLER COMPUTING INC1 citations73

US11997853B1May 28, 2024

1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

KEPLER COMPUTING INC1 citations73

US11978762B1May 7, 2024

Planar capacitors with non-linear polar material staggered on a shared electrode

KEPLER COMPUTING INC1 citations73

US11955153B1Apr 9, 2024

Multi-element gain memory bit-cell having stacked and folded planar memory elements with and without offset

KEPLER COMPUTING INC1 citations73

US11910618B1Feb 20, 2024

Multi-element ferroelectric gain memory bit-cell having stacked and folded non-planar capacitors

KEPLER COMPUTING INC1 citations73

US11903219B1Feb 13, 2024

Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors

KEPLER COMPUTING INC1 citations73

US11784164B2Oct 10, 2023

3D stacked compute and memory with copper-to-copper hybrid bond

KEPLER COMPUTING INC3 citations73

US11741428B1Aug 29, 2023

Iterative monetization of process development of non-linear polar material and devices

KEPLER COMPUTING INC2 citations73

US11699699B1Jul 11, 2023

Multi-function threshold gate with adaptive threshold and stacked planar ferroelectric capacitors

KEPLER COMPUTING INC3 citations73

US11527278B1Dec 13, 2022

Non-linear polar material based memory bit-cell with multi-level storage by applying different time pulse widths

KEPLER COMPUTING INC0 citations73

US12334918B1Jun 17, 2025

Stacked non-planar capacitors based multi-function linear threshold gate with input based adaptive threshold

KEPLER COMPUTING INC0 citations63

US12322743B1Jun 3, 2025

Multi-function threshold gate with input based adaptive threshold and with stacked non-planar paraelectric capacitors

KEPLER COMPUTING INC0 citations63

US12283571B1Apr 22, 2025

Ultra high-bandwidth artificial intelligence (AI) processor with DRAM under the processor

KEPLER COMPUTING INC0 citations63

US12218045B1Feb 4, 2025

Stacked planar capacitors based multi-function linear threshold gate with input based adaptive threshold

KEPLER COMPUTING INC0 citations63

US11985831B1May 14, 2024

Multi-function threshold gate with input based adaptive threshold and with stacked non-planar ferroelectric capacitors

KEPLER COMPUTING INC0 citations63

US11810608B1Nov 7, 2023

Manganese or scandium doped multi-element non-linear polar material gain memory bit-cell

KEPLER COMPUTING INC0 citations63

US11605411B1Mar 14, 2023

Method of forming stacked ferroelectric planar capacitors in a memory bit-cell

KEPLER COMPUTING INC0 citations63

US11532342B1Dec 20, 2022

Non-linear polar material based differential multi-memory element bit-cell

KEPLER COMPUTING INC0 citations63

US11514966B1Nov 29, 2022

Non-linear polar material based multi-memory element bit-cell with multi-level storage

KEPLER COMPUTING INC0 citations63

US11514967B1Nov 29, 2022

Non-linear polar material based differential multi-memory element gain bit-cell

KEPLER COMPUTING INC0 citations63

US12412611B1Sep 9, 2025

Time decoupled write operations for non-linear polar material based memory

KEPLER COMPUTING INC0 citations62

US12147941B2Nov 19, 2024

Iterative monetization of precursor in process development of non-linear polar material and devices

KEPLER COMPUTING INC0 citations62

Showing the top 50 of 54 patents by PatentIndex Score.

OLAOSEBIKAN DEBO

Patents

3D stack of accelerator die and multi-core processor die

Stacked ferroelectric non-planar capacitors in a memory bit-cell

3D integrated ultra high-bandwidth multi-stacked memory

3D integrated ultra high-bandwidth memory

Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging

Non-linear polar material based memory bit-cell with multi-level storage by applying different voltage levels

High-density low voltage multi-element ferroelectric gain memory bit-cell with pillar capacitors

Stacked ferroelectric planar capacitors in a memory bit-cell

Method of forming stacked ferroelectric non- planar capacitors in a memory bit-cell

3D stack of split graphics processing logic dies

Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer

Ferroelectric memory chiplet in a multi-dimensional packaging

Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic

Method and apparatus for managing power in a multi-dimensional packaging

Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic

Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging

Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging

Method to segregate logic and memory into separate dies for thermal management in a multi-dimensional packaging

Multi-function threshold gate with adaptive threshold and stacked planar paraelectric capacitors

High-density low voltage multi-element ferroelectric gain memory bit-cell with planar capacitors

Method and apparatus for cycle-by-cycle clock gating of ferroelectric or paraelectric logic and CMOS based logic

Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors with lateral offset

High-density low voltage ferroelectric memory bit-cell

Multi-input threshold gate having stacked and folded non-planar capacitors

Method of forming an artificial intelligence processor with three-dimensional stacked memory

Memory bit-cell with stacked and folded planar capacitors

One transistor and N memory element based memory bit-cell having stacked and folded planar memory elements with and without offset

Multi-input threshold gate having stacked and folded planar capacitors with and without offset

1TnC memory bit-cell having stacked and folded non-planar capacitors

1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset

Planar capacitors with non-linear polar material staggered on a shared electrode

Multi-element gain memory bit-cell having stacked and folded planar memory elements with and without offset

Multi-element ferroelectric gain memory bit-cell having stacked and folded non-planar capacitors

Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors

3D stacked compute and memory with copper-to-copper hybrid bond

Iterative monetization of process development of non-linear polar material and devices

Multi-function threshold gate with adaptive threshold and stacked planar ferroelectric capacitors

Non-linear polar material based memory bit-cell with multi-level storage by applying different time pulse widths

Stacked non-planar capacitors based multi-function linear threshold gate with input based adaptive threshold

Multi-function threshold gate with input based adaptive threshold and with stacked non-planar paraelectric capacitors

Ultra high-bandwidth artificial intelligence (AI) processor with DRAM under the processor

Stacked planar capacitors based multi-function linear threshold gate with input based adaptive threshold

Multi-function threshold gate with input based adaptive threshold and with stacked non-planar ferroelectric capacitors

Manganese or scandium doped multi-element non-linear polar material gain memory bit-cell

Method of forming stacked ferroelectric planar capacitors in a memory bit-cell

Non-linear polar material based differential multi-memory element bit-cell

Non-linear polar material based multi-memory element bit-cell with multi-level storage

Non-linear polar material based differential multi-memory element gain bit-cell

Time decoupled write operations for non-linear polar material based memory

Iterative monetization of precursor in process development of non-linear polar material and devices