Inventor
DHRUVANARAYAN SRIVATHSA
US18 patents
⚠️ This page may combine multiple inventors who share the name “DHRUVANARAYAN SRIVATHSA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
BAREFOOT NETWORKS INC
7 patentsUS10686735B1Jun 16, 2020
Packet reconstruction at deparser
BAREFOOT NETWORKS INC30 citations92
US10757028B1Aug 25, 2020
Configurable forwarding element deparser
BAREFOOT NETWORKS INC9 citations82
US10694006B1Jun 23, 2020
Generation of descriptive data for packet fields
BAREFOOT NETWORKS INC10 citations82
US11425058B2Aug 23, 2022
Generation of descriptive data for packet fields
BAREFOOT NETWORKS INC2 citations71
US10949199B1Mar 16, 2021
Copying packet data to mirror buffer
BAREFOOT NETWORKS INC1 citations62
US12375588B2Jul 29, 2025
Generation of descriptive data for packet fields
BAREFOOT NETWORKS INC0 citations60
US10848429B1Nov 24, 2020
Queue scheduler control via packet data
BAREFOOT NETWORKS INC0 citations52
SIMA TECH INC
7 patentsUS11321607B2May 3, 2022
Machine learning network implemented by statically scheduled instructions, with compiler
SIMA TECH INC9 citations81
US11488066B2Nov 1, 2022
Efficient convolution of multi-channel input samples with multiple kernels
SIMA TECH INC2 citations72
US11403519B2Aug 2, 2022
Machine learning network implemented by statically scheduled instructions, with system-on-chip
SIMA TECH INC2 citations68
US11886981B2Jan 30, 2024
Inter-processor data transfer in a machine learning accelerator, using statically scheduled instructions
SIMA TECH INC1 citations61
US11354570B2Jun 7, 2022
Machine learning network implemented by statically scheduled instructions, with MLA chip
SIMA TECH INC1 citations58
US12333351B2Jun 17, 2025
Synchronization of processing elements that execute statically scheduled instructions in a machine learning accelerator
SIMA TECH INC0 citations50
US11631001B2Apr 18, 2023
Heterogeneous computing on a system-on-chip, including machine learning inference
SIMA TECH INC0 citations50