Inventor

AMBROLADZE EKATERINA M

US47 patents

⚠️ This page may combine multiple inventors who share the name “AMBROLADZE EKATERINA M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AMBROLADZE EKATERINA M

IBM

Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index

User-controlled targeted cache purge

Increased bandwidth of ordered stores in a non-uniform memory subsystem

Increased bandwidth of ordered stores in a non-uniform memory subsystem

Maintaining order with parallel access data streams

Eliminate corrupted portions of cache during runtime

Eliminate corrupted portions of cache during runtime

Non-disruptive clearing of varying address ranges from cache

Non-disruptive clearing of varying address ranges from cache

Non-disruptive clearing of varying address ranges from cache

Designated cache data backup during system operation

Multilevel cache eviction management

Configuration based cache coherency protocol selection

Castout handling in a distributed cache topology

Preinstall of partial store cache lines

Efficient eviction of whole set associated cache or selected range of addresses

Eliminate corrupted portions of cache during runtime

Bitline deletion

Dynamic cache correction mechanism to allow constant access to addressable index

High performance cache directory error correction code

Configuration based cache coherency protocol selection

Configuration based cache coherency protocol selection

Configuration based cache coherency protocol selection

Multiprocessor cache buffer management

Input/output (I/O) store protocol for pipelining coherent operations

Efficient inclusive cache management

Configuration based cache coherency protocol selection

Monitoring processing time in a shared pipeline

Multiprocessor cache buffer management

Bidirectional ring-based interconnection networks having a cross bar for multiprocessors

Coherent cache with simultaneous data requests in same addressable index

Achieving high bandwidth on ordered direct memory access write stream into a processor cache

Data processing apparatus and method

AMBROLADZE EKATERINA M

On demand allocation of cache buffer slots

Dynamic multi-level cache including resource access fairness scheme

Bitline deletion

Dynamic pipeline cache error correction

Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable index

Bitline deletion

Dynamic cache correction mechanism to allow constant access to addressable index

Monitoring processing time in a shared pipeline

Method for optimizing sequential data fetches in a computer system

Error detection and recovery in a shared pipeline

Managing dataflow in a temporary memory

BERGER DEANNA POSTLES DUNN

Diagnostic data collection and storage put-away station in a multiprocessor system

Multiple level linked LRU priority

PAPAZOVA VESSELINA K

Cache coherency protocol with built in avoidance for conflicting responses