Inventor

DESOLI GIUSEPPE

IT50 patents

⚠️ This page may combine multiple inventors who share the name “DESOLI GIUSEPPE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DESOLI GIUSEPPE

ST MICROELECTRONICS SRL

Reconfigurable interconnect

Tool to create a reconfigurable interconnect framework

Arithmetic unit for deep learning acceleration

Configurable accelerator framework including a stream switch having a plurality of unidirectional stream links

Reconfigurable interconnect

Convolution acceleration with embedded vector decompression

Data volume sculptor for deep learning acceleration

Hardware accelerator engine

Acceleration unit for a deep learning engine

Tool to create a reconfigurable interconnect framework

Elements for in-memory compute

Data volume sculptor for deep learning acceleration

Reconfigurable interconnect

Vector quantization decoding hardware unit for real-time dynamic decompression for parameters of neural networks

Method of operating neural networks, corresponding network, apparatus and computer program product

Tagged memory operated at lower VMIN in error tolerant system

Computing system power management device, system and method

Arithmetic unit for deep learning acceleration

Data volume sculptor for deep learning acceleration

Variable clock adaptation in neural network processors

Convolution acceleration with embedded vector decompression

Tagged memory operated at lower vmin in error tolerant system

Elements for in-memory compute

Computing system power management device, system and method

Tagged memory operated at lower vmin in error tolerant system

Deep convolutional network heterogeneous architecture

Vector quantization decoding hardware unit for real-time dynamic decompression for parameters of neural networks

Programmable hardware accelerator controller

Convolutional network hardware accelerator device, system and method

Neural network hardware accelerator circuit with requantization circuits

Tool to create a reconfigurable interconnect framework

Reconfigurable hardware buffer in a neural networks accelerator framework

Hardware accelerator method, system and device

Artificial neural network processing methods and system

ST MICROELECTRONICS INT NV

Adaptive buffer sharing in multi-core reconfigurable streaming-based architectures

Pooling unit for deep learning acceleration

Pooling unit for deep learning acceleration

Streaming access memory device, system and method

Self-contained and configurable debugging mechanism for stream-based hardware accelerators

Configurable stream switch with virtual channels for the sharing of I/O ports in stream-based architectures

Stream-based modular and scalable HW accelerator sub-system with design-time parametric reconfigurable NPU cores

HEWLETT PACKARD DEVELOPMENT CO

Systems and methods for integrating emulated and native code

Synchronization of asynchronous emulated interrupts

System and method for facilitating profiling an application

System and method for decoding and executing program binaries

Transparent remote data storage device and method

Networked client-server architecture for transparently transforming and executing applications

HEWLETT PACKARD CO

Radial and pruned radial interpolation

PAPARIELLO FRANCESCO

Simulation system for implementing computing device models in a multi-simulation environment

DESOLI GIUSEPPE

Data stream flow controller and computing system architecture comprising such a flow controller