Inventor
PADHYE MILIND P
US8 patents
Patents
8 patentsUS7183825B2Feb 27, 2007
State retention within a data processing system
FREESCALE SEMICONDUCTOR INC69 citations97
US7123068B1Oct 17, 2006
Flip-flop circuit having low power data retention
FREESCALE SEMICONDUCTOR INC33 citations90
US7138842B2Nov 21, 2006
Flip-flop circuit having low power data retention
FREESCALE SEMICONDUCTOR INC37 citations87
US8020017B2Sep 13, 2011
Management of power domains in an integrated circuit
FREESCALE SEMICONDUCTOR INC21 citations86
US7365596B2Apr 29, 2008
State retention within a data processing system
FREESCALE SEMICONDUCTOR INC11 citations83
US7346820B2Mar 18, 2008
Testing of data retention latches in circuit devices
FREESCALE SEMICONDUCTOR INC12 citations80
US7779284B2Aug 17, 2010
Techniques for operating a processor subsystem to service masked interrupts during a power-down sequence
FREESCALE SEMICONDUCTOR INC4 citations60
US7612577B2Nov 3, 2009
Speedpath repair in an integrated circuit
FREESCALE SEMICONDUCTOR INC4 citations60