Inventor

VENKATASUBRAMANIAN RAMAKRISHNAN

US44 patents

⚠️ This page may combine multiple inventors who share the name “VENKATASUBRAMANIAN RAMAKRISHNAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VENKATASUBRAMANIAN RAMAKRISHNAN

TEXAS INSTRUMENTS INC

Highly integrated scalable, flexible DSP megamodule architecture

Highly integrated scalable, flexible DSP megamodule architecture

Highly integrated scalable, flexible DSP megamodule architecture

Lookahead priority collection to support priority elevation

Delay fault testing using distributed clock dividers

Servicing CPU demand requests with inflight prefetchs

On-chip power-domain supply drooping for low voltage idle/standby management

Lookahead priority collection to support priority elevation

Highly integrated scalable, flexible DSP megamodule architecture

Lookahead priority collection to support priority elevation

Non-volatile memory compression for memory repair

Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors

Hiding page translation miss latency in program memory controller by next page prefetch on crossing page boundary

Using L1 cache as re-order buffer

Power switch with source-bias mode for on-chip powerdomain supply drooping

Servicing CPU demand requests with inflight prefetches

Non-volatile memory compression for memory repair

Zero latency prefetching in caches

Servicing CPU demand requests with inflight prefetches

Integrated circuit with high-speed clock bypass before reset

Non-volatile memory compression for memory repair

Servicing CPU demand requests with inflight prefetches

Zero latency prefetching in caches

Integrated circuit with high-speed clock bypass before reset

Zero latency prefetching in caches

Integer and half clock step division digital variable clock divider

Hiding page translation miss latency in program memory controller by selective page miss translation prefetch

Process variability tolerant programmable memory controller for a pipelined memory system

Electrical and logic isolation for systems on a chip

Servicing CPU demand requests with inflight prefetches

Using L1 cache as re-order buffer

Power switch with source-bias mode for on-chip powerdomain supply drooping

Local page translation and permissions storage for the page window in program memory controller

DAMODARAN RAGURAM

Requester based transaction status reporting in a system with multi-level memory

Asynchronous clock dividers to reduce on-chip variations of clock timing

Multi-port register file with an input pipelined architecture with asynchronous reads and localized feedback

VENKATASUBRAMANIAN RAMAKRISHNAN

Integer and half clock step division digital variable clock divider

Reducing current leakage in L1 program memory

Clock control of pipelined memory for improved delay fault testing

CHACHAD ABHIJEET ASHOK

Efficient level two memory banking to improve performance for multiple source traffic and enable deeper pipelining of accesses by reducing bank stalls

Process variability tolerant programmable memory controller for a pipelined memory system

COGNIZANT TECHNOLOGY SOLUTIONS INDIA PVT LTD

System and method for hosting mobile devices for testing in a cloud computing environment

COGNIZANT TECH SOLUTIONS INDIA PVT LTD

System and method for automatically generating software testing scripts from test cases

ALTERA CORP

Interface/unicast for test content, firmware, and software delivery