Inventor
FASTENAU JOEL M
US11 patents
⚠️ This page may combine multiple inventors who share the name “FASTENAU JOEL M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
9 patentsUS7601980B2Oct 13, 2009
Dopant confinement in the delta doped layer using a dopant segregation barrier in quantum well structures
INTEL CORP24 citations92
US7573059B2Aug 11, 2009
Dislocation-free InSb quantum well structure on Si using novel buffer architecture
INTEL CORP41 citations92
US7494911B2Feb 24, 2009
Buffer layers for device isolation of devices grown on silicon
INTEL CORP19 citations92
US7851780B2Dec 14, 2010
Semiconductor buffer architecture for III-V devices on silicon substrates
INTEL CORP14 citations83
US7687799B2Mar 30, 2010
Methods of forming buffer layer architecture on silicon and structures formed thereby
INTEL CORP8 citations83
US7566898B2Jul 28, 2009
Buffer architecture formed on a semiconductor wafer
INTEL CORP17 citations83
US8034675B2Oct 11, 2011
Semiconductor buffer architecture for III-V devices on silicon substrates
INTEL CORP0 citations51
US7851781B2Dec 14, 2010
Buffer layers for device isolation of devices grown on silicon
INTEL CORP0 citations51
US7790536B2Sep 7, 2010
Dopant confinement in the delta doped layer using a dopant segregration barrier in quantum well structures
INTEL CORP0 citations51