Inventor

LUNING SCOTT

US54 patents

⚠️ This page may combine multiple inventors who share the name “LUNING SCOTT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LUNING SCOTT

ADVANCED MICRO DEVICES INC

Integrated circuit and method for its manufacture

Low-K sub spacer pocket formation for gate capacitance reduction

Advanced technique for forming a transistor having raised drain and source regions

Control trimming of hard mask for sub-100 nanometer transistor gate

CMOS semiconductor device comprising graded junctions with reduced junction capacitance

CMOS processing employing zero degree halo implant for P-channel transistor

Very low thermal budget channel implant process for semiconductors

Silicidation and deep source-drain formation prior to source-drain extension formation

Stressed field effect transistor and methods for its fabrication

Technique for forming transistors having raised drain and source regions with different heights

Composite spacer liner for improved transistor performance

Method to form narrow structure using double-damascene process

Fabrication of raised source-drain transistor devices

Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device

Flash EEPROM memory with reduced column leakage current

Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device

Method of making flash EEPROM memory with reduced column leakage current

Self-aligned implant energy modulation for shallow source drain extension formation

Method of manufacturing a semiconductor component

Method for differential trenching in conjunction with differential fieldox growth

Oxide spacers as solid sources for gallium dopant introduction

Method of forming semiconductor device comprising a drain region with a graded N-LDD junction with increased HCI lifetime

CMOS semiconductor device comprising graded junctions with reduced junction capacitance

MOSFET with asymmetrical extension implant

Selective epitaxy to reduce gate/gate dielectric interface roughness

Process to separate the doping of polygate and source drain regions in dual gate field effect transistors

Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device

Shallow drain extension formation by angled implantation

Structure and method for exposing photoresist

Method and arrangement for reducing source/drain resistance with epitaxial growth

Technique for forming a transistor having raised drain and source regions with a reduced number of process steps

Differential implant oxide process

Semiconductor processing employing a semiconductor spacer

Methods for fabricating a stress enhanced semiconductor device having narrow pitch and wide pitch transistors

Technique for forming a transistor having raised drain and source regions with a tri-layer hard mask for gate patterning

Method for exposing photoresist

GLOBALFOUNDRIES INC

Methods for fabricating non-planar semiconductor devices having stress memory

Semiconductor device with stressed fin sections, and related fabrication methods

FinFET structures with stress-inducing source/drain-forming spacers and methods for fabricating the same

Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods

Method, apparatus, and system for using a cover mask for enabling metal line jumping over MOL features in a standard cell

Method, apparatus, and system for using a cover mask for enabling metal line jumping over MOL features in a standard cell

IBM

Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs

Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs

Stacking fault reduction in epitaxially grown silicon

Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs

LUNING SCOTT

Semiconductor device with stressed fin sections

Methods for fabricating FinFET semiconductor devices using L-shaped spacers

YANG FRANK BIN

Embedded silicon germanium source drain structure with reduced silicide encroachment and contact resistance and enhanced channel mobility

WAITE ANDREW M

Stressed field effect transistor and methods for its fabrication