Inventor

LEE PETER W

US84 patents

⚠️ This page may combine multiple inventors who share the name “LEE PETER W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE PETER W

APLUS FLASH TECHNOLOGY INC

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Parallel channel programming scheme for MLC flash memory

Low voltage, low current hot-hole injection erase and hot-electron programmable flash memory with enhanced endurance

Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications

Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations

Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device

Set of three level concurrent word line bias conditions for a nor type flash memory array

Three step write process used for a nonvolatile NOR type EEPROM memory

Positive/negative high voltage charge pump system

Node-precise voltage regulation for a MOS memory system

3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Flash memory array structure suitable for multiple simultaneous operations

Node-precise voltage regulation for a MOS memory system

Flash memory with high speed erasing structure using thin oxide semiconductor devices

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Combination nonvolatile integrated memory system using a universal technology most suitable for high-density, high-flexibility and high-security sim-card, smart-card and e-passport applications

Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations

Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations

Unified non-volatile memory device and method for integrating NOR and NAND-type flash memory and EEPROM device on a single substrate

Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Flash memory array structure suitable for multiple simultaneous operations

Non-volatile semiconductor memory having split-gate memory cells mirrored in a virtual ground configuration

Highly-integrated flash memory and mask ROM array architecture

Stacked gate flash memory cell with reduced disturb conditions

Flash memory array for multiple simultaneous operations

Flash memory array structure suitable for multiple simultaneous operations

Multiple level flash memory

Array architecture and process flow of nonvolatile memory devices for mass storage applications

Reversed split-gate cell array

Erase condition for flash memory

Flash memory with novel bitline decoder and sourceline latch

APLUS INTEGRATED CIRCUITS INC

Flash memory wordline decoder with overerase repair

Bit-refreshable method and circuit for refreshing a nonvolatile flash memory

OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array

Memory device with on-chip manufacturing and memory cell defect detection capability

Flash memory read/write controller

Flash memory with row redundancy

Flash EEPROM worldline decoder

Flat-cell ROM and decoder

APPLIED MATERIALS INC

Apparatus for improving film stability of halogen-doped silicon oxide films

Two step process for forming void-free oxide layer over stepped surface of semiconductor wafer

Method and apparatus for improving film stability of halogen-doped silicon oxide films

Method and apparatus for forming a thin polymer layer on an integrated circuit structure

Boron phosphorus silicate glass composite layer on semiconductor wafer

Method for forming a boron phosphorus silicate glass composite layer on a semiconductor wafer