Inventor

YANG CHING-JUNG

TW71 patents

⚠️ This page may combine multiple inventors who share the name “YANG CHING-JUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YANG CHING-JUNG

TAIWAN SEMICONDUCTOR MFG CO LTD

3DIC structure with protective structure and method of fabricating the same

Semiconductor structure and manufacturing method thereof

3DIC structure with protective structure and method of fabricating the same and package

Integrated circuit structure and seal ring structure

Integrated fan-out (InFO) package structures and methods of forming same

Method and apparatus for packaging pad structure

Die stack structure with hybrid bonding structure and method of fabricating the same and package

Plurality of different size metal layers for a pad structure

Package with solder regions aligned to recesses

Self-alignment structure for wafer level chip scale package

Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices

Semiconductor structure including interconnection to probe pad with probe mark

Semiconductor structure

Package structure with protective structure and method of fabricating the same

Plurality of different size metal layers for a pad structure

Semiconductor package with shared barrier layer in redistribution and via

Semiconductor structure including interconnection to probe pad with probe mark and method of manufacturing the same

Integrated circuit device with through interconnect via and methods of manufacturing the same

Method of fabricating semiconductor structure

Bump structure and fabricating method thereof

Semiconductor packaging structure including interconnection to probe pad with probe mark and method of manufacturing the same

Plurality of different size metal layers for a pad structure

Integrated circuit component package and method of fabricating the same

Hollow metal pillar packaging scheme

Method for manufacturing semiconductor structure

Package with solder regions aligned to recesses

Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices

Semiconductor device and fabricating method thereof

Package with solder regions aligned to recesses

Semiconductor structure and manufacturing method thereof

Alignment structures and methods of forming same

MIM capacitor and method forming the same

Semiconductor structure having an anti-arcing pattern disposed on a passivation layer and a post passivation layer disposed on the anti-arcing pattern

Semiconductor structure having an anti-arcing pattern disposed on a passivation layer and method of fabricating the semiconductor structure

Semiconductor structure and method of forming

Semiconductor structure

Semiconductor structure and manufacturing method thereof

Method of manufacturing die stack structure

Semiconductor package with shared barrier layer in redistribution and via and method of manufacturing the same

Semiconductor structure including interconnection to probe pad with probe mark

Semiconductor structure

Semiconductor structure and manufacturing method thereof

Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices

Semiconductor device and manufacturing method thereof

Conductive bump of a semiconductor device and fabricating method thereof cross reference to related applications

TAIWAN SEMICONDUCTOR MFG

Metal insulator metal capacitor and method for making the same

Reducing delamination between an underfill and a buffer layer in a bond structure

CHEN HSIEN-WEI

Probe pad on a corner stress relief region in a semiconductor chip

SHAO TUNG-LIANG

Measurement of electrical and mechanical characteristics of low-K dielectric in a semiconductor device

LIU YU-WEN

Reinforcement structure for flip-chip packaging