Inventor

CHANG MARK S

US50 patents

⚠️ This page may combine multiple inventors who share the name “CHANG MARK S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG MARK S

ADVANCED MICRO DEVICES INC

Processing techniques for achieving production-worthy, low dielectric, low dielectric, low interconnect resistance and high performance IC

Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance

Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS

Photosensitive polymeric memory elements

Polymer memory device formed in via opening

Methods of forming passive layers in organic memory cells

Method(s) facilitating formation of memory cell(s) and patterned conductive

Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance

Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device

Photosensitive polymeric memory elements

CVD organic polymer film for advanced gate patterning

Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices

Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer

Semiconductor device with self-aligned contacts using a liner oxide layer

Self-aligning vias for semiconductors

Method for shaping photoresist mask to improve high aspect ratio ion implantation

Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS

Sidewall formation for high density polymer memory element array

Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication

RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist

Method and system for decreasing the spaces between wordlines

Plasma treatment for polymer removal after via etch

Multi-cell organic memory element and methods of operating and fabricating

Flash memory having improved core field isolation in select gate regions

Isolation trench fill process

Method and system for processing a semiconductor device

Method for manufacturing semiconductors with self-aligning vias

Method for fabrication of shallow isolation trenches with sloped wall profiles

System and method of forming a passive layer by a CMP process

Flash memory array and a method and system of fabrication thereof

Shallow trench isolation spacer for weff improvement

Method and system for providing contacts with greater tolerance for misalignment in a flash memory

Stepper alignment mark formation with dual field oxide process

Self-aligned silicide contacts formed from deposited silicon

Flash memory device and a method of fabrication thereof

Method for patterning narrow gate lines

Method and system for etching tunnel oxide to reduce undercutting during memory array fabrication

Method and system for processing a semiconductor device

Method and system for fabricating a flash memory array

Etch process for CD reduction of arc material

Integrated circuit with metal and semi-conducting gate

Stepper alignment mark formation with dual field oxide process

Method and system for providing shallow trench profile shaping through spacer and etching

CHANG MARK S

Method and system for providing contact to a first polysilicon layer in a flash memory device

Method and system for providing contact to a first polysilicon layer in a flash memory device

Method and system for providing contact to a first polysilicon layer in a flash memory device

SPANSION LLC

Shallow trench isolation approach for improved STI corner rounding

Method of making an organic memory cell

HEWLETT PACKARD CO

Multilayer photoresist process utilizing an absorbant dye

HUI ANGELA T

Integrated circuit system with metal and semi-conducting gate