Inventor

LIU YOWJUANG W

US71 patents

⚠️ This page may combine multiple inventors who share the name “LIU YOWJUANG W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU YOWJUANG W

ADVANCED MICRO DEVICES INC

Trench-gated vertical combination JFET and MOSFET devices

Method for forming advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits

Reverse damascene via structures

Advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits

Double density non-volatile memory cells

Fully recessed semiconductor device and method for low power applications with single wrap around buried drain region

MOS transistor with low-k spacer to suppress capacitive coupling between gate and source/drain extensions

High quality isolation for high density and high performance integrated circuits

Bar field effect transistor

Reverse CMOS method for dual isolation semiconductor device

Trench-gated vertical CMOS device

SRAM cell having single layer polysilicon thin film transistors

Hybrid of local oxidation of silicon isolation and trench isolation for a semiconductor device

Post-gate LOCOS

Trench isolation of field effect transistors

Method of making semiconductor device with self-aligned insulator

Semiconductor-on-insulator body-source contact and method

Semiconductor-on-insulator body-source contact and method

Fully recessed semiconductor method for low power applications

Method for fabricating a trench-gated vertical CMOS device

MOS transistor with minimal overlap between gate and source/drain extensions

Trenched gate semiconductor device and method for low power applications

Method for post transistor isolation

Method for fabricating a dual material gate of a short channel field effect transistor

Fully recessed semiconductor device

Double density non-volatile memory cells

Trenched gate metal oxide semiconductor device and method

C-V method to extract lateral channel doping profiles of MOSFETs

Three-dimensional non-volatile memory

Isolation boundaries in flash memory cores

Advanced etching method for VLSI fabrication

Trenched gate non-volatile semiconductor device and method with corner doping and sidewall doping

Nitridation assisted polysilicon sidewall protection in self-aligned shallow trench isolation

Integrated circuit having improved polysilicon resistor structures

Three-dimensional complementary field effect transistor process

Method of fabricating field effect transistors having lightly doped drain regions

Method of making simplified LDD and source/drain formation in advanced CMOS integrated circuits using implantation through well mask

Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers

Method of making trench isolation structures with oxidized silicon regions

Method for measuring gate length and drain/source gate overlap

Trench isolation structures with oxidized silicon regions and method for making the same

Double density V nonvolatile memory cell

Process for producing optimum intrinsic, long channel, and short channel mos devices in vlsi structures

Semiconductor device with self-aligned insulator

Trench isolation of field effect transistors

Trenched gate non-volatile semiconductor method with the source/drain regions spaced from the trench by sidewall dopings

Sidewall spacer for protecting tunnel oxide during isolation trench formation in self-aligned flash memory core

Method of fabricating FET or CMOS transistors using MeV implantation

Method and apparatus for determining the robustness and incident angle sensitivity of memory cells to alpha-particle/cosmic ray induced soft errors

ALTERA CORP

Apparatus and methods for integrated circuit with devices with body contact and devices with electrostatic discharge protection