Inventor

LE HUNG QUI

US100 patents

⚠️ This page may combine multiple inventors who share the name “LE HUNG QUI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LE HUNG QUI

IBM

Method and apparatus for patching problematic instructions in a microprocessor using software interrupts

System and method for managing the execution of instruction groups having multiple executable instructions

Branch encoding before instruction cache write

Instruction grouping history on fetch-side dispatch group formation

Content addressable storage apparatus and register mapper architecture

Method and system for managing registers in a data processing system supports out-of-order and speculative instruction execution

Method and system for dynamically shared completion table supporting multiple threads in a processing system

Recovery from hang condition in a microprocessor

Queuing method and apparatus for facilitating the rejection of sequential instructions in a processor

Issuing instructions in a processor supporting out-of-order execution

Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched

System and method for executing store instructions

Parallel slice processor with dynamic instruction stream mapping

Processing of multiple instruction streams in a parallel slice processor

Processing of multiple instruction streams in a parallel slice processor

Parallel slice processor with dynamic instruction stream mapping

Method and system for efficiently restoring a processor&#39;s execution state following an interrupt caused by an interruptible instruction

System and method for dispatching groups of instructions using pipelined register renaming

Mechanism for self-initiated instruction issuing and method therefor

Data processing system and method for capturing history buffer data

Concurrent execution of machine context synchronization operations and non-interruptible instructions

Data stream prefetching in a microprocessor

Branch lookahead prefetch for microprocessors

Using a modified value GPR to enhance lookahead prefetch

Data stream prefetching in a microprocessor

Instruction group formation and mechanism for SMT dispatch

Mechanism to reduce instruction cache miss penalties and methods therefor

Assigning a group tag to an instruction group wherein the group tag is recorded in the completion table along with a single instruction address for the group to facilitate in exception handling

Compressed string and multiple generation engine

Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPs

Method and system for optimizing the fetching of dispatch groups in a superscalar processor

Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution

Apparatus and method for reducing the number of rename registers required in the operation of a processor

Method and apparatus for reducing the number of rename registers in a processor supporting out-of-order execution

Dispatching instructions in a processor supporting out-of-order execution

Method and apparatus for condensed history buffer

Method and apparatus for improved recovery of processor state using history buffer

Method and apparatus for writing information to registers in a data processing system using a number of registers for processing instructions

Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions

Processor instruction retry recovery

Superscalar processor and method for incrementally issuing store instructions

Method and system for reducing average branch resolution time and effective misprediction penalty in a processor

Reconfigurable parallel execution and load-store slice processor

Reconfigurable processing method with modes controlling the partitioning of clusters and cache slices

Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors

Load lookahead prefetch for microprocessors

System for rejecting and reissuing instructions after a variable delay time period

Method and apparatus for multi-stage hang recovery in an out-of-order microprocessor

ABERNATHY CHRISTOPHER MICHAEL

Selecting fixed-point instructions to issue on load-store unit

HELLER JR THOMAS J

Transactional memory system which employs thread assists using address history tables

Method and system for efficiently restoring a processor's execution state following an interrupt caused by an interruptible instruction