Inventor

NADEAU-DOSTIE BENOIT

CA49 patents

⚠️ This page may combine multiple inventors who share the name “NADEAU-DOSTIE BENOIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NADEAU-DOSTIE BENOIT

LOGICVISION INC

Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same

Method and circuit for collecting memory failure information

Scan test method for providing real time identification of failing test patterns and test bist controller for use therewith

Method and apparatus for testing high performance circuits

Test access circuit and method of accessing embedded test controllers in integrated circuit modules

Clock skew management method and apparatus

Asynchronous interface

Method for testability analysis and test point insertion at the RT-level of a hardware development language (HDL) specification

Method and apparatus for testing circuits with multiple clocks

Method of testing at-speed circuits having asynchronous clocks and controller for use therewith

Method for at-speed testing of memory interface using scan

Clock controller for at-speed testing of scan circuits

Method for scan testing of digital circuit, digital circuit for use therewith and program product for incorporating test methodology into circuit description

Method of masking corrupt bits during signature analysis and circuit for use therewith

Method for testing circuits with tri-state drivers and circuit for use therewith

Method and apparatus for controlling power level during BIST

Method and apparatus for scan testing digital circuits

Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby

Boundary scan with strobed pad driver enable

Method and circuit for at-speed testing of scan circuits

Method and test circuit for testing memory internal write enable

Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby

Method for collecting failure information for a memory using an embedded test controller

Method and circuitry for controlling clocks of embedded blocks during logic bist test mode

Memory repair analysis method and circuit

Method and program product for designing hierarchical circuit for quiescent current testing

Method of and program product for performing gate-level diagnosis of failing vectors

Memory repair circuit and method

Clocking methodology for at-speed testing of scan circuits with synchronous clocks

SIEMENS IND SOFTWARE INC

Configurable built-in self-repair chain for fast repair data loading

Error-correcting code-assisted memory repair

Method and apparatus for processing memory repair information

Asynchronous interface for transporting test-related data via serial channels

Memory built-in self-test with automated reference trim feedback for memory sensing

Read-only memory diagnosis and repair

Reference bits test and repair using memory built-in self-test

LOGIC VISION INC

Method and apparatus for high-speed interconnect testing

Bist architecture for measurement of integrated circuit delays

Fault insertion method, boundary scan cells, and integrated circuit for use therewith

Method and apparatus for testing multi-port memory

Method and apparatus for testing multi-port memory using shadow read

NORTHERN TELECOM LTD

Multiple clock rate test apparatus for testing digital systems

Serial testing technique for embedded memories

Integrated circuit testing method and apparatus and integrated circuit devices for use therewith

Scan cell for weighted random pattern generation and method for its operation

MENTOR GRAPHICS CORP

Method and apparatus for storing and distributing memory repair information

(unassigned)

Method and program product for modeling circuits with latch based design

NADEAU-DOSTIE BENOIT

Methods for at-speed testing of memory interface

RAJSKI JANUSZ

Test generator for low power built-in self-test