Inventor
PHAM TUAN DUC
US26 patents
⚠️ This page may combine multiple inventors who share the name “PHAM TUAN DUC”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ADVANCED MICRO DEVICES INC
20 patentsUS6034395AMar 7, 2000
Semiconductor device having a reduced height floating gate
ADVANCED MICRO DEVICES INC21 citations92
US6027998AFeb 22, 2000
Method for fully planarized conductive line for a stack gate
ADVANCED MICRO DEVICES INC48 citations92
US6867097B1Mar 15, 2005
Method of making a memory cell with polished insulator layer
ADVANCED MICRO DEVICES INC45 citations91
US6969654B1Nov 29, 2005
Flash NVROM devices with UV charge immunity
ADVANCED MICRO DEVICES INC12 citations84
US6509604B1Jan 21, 2003
Nitridation barriers for nitridated tunnel oxide for circuitry for flash technology and for LOCOS/STI isolation
ADVANCED MICRO DEVICES INC15 citations84
US6369416B1Apr 9, 2002
Semiconductor device with contacts having a sloped profile
ADVANCED MICRO DEVICES INC16 citations84
US6689682B1Feb 10, 2004
Multilayer anti-reflective coating for semiconductor lithography
ADVANCED MICRO DEVICES INC9 citations74
US6605511B2Aug 12, 2003
Method of forming nitridated tunnel oxide barriers for flash memory technology circuitry and STI and LOCOS isolation
ADVANCED MICRO DEVICES INC11 citations74
US6465835B1Oct 15, 2002
Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate
ADVANCED MICRO DEVICES INC7 citations74
US6448608B1Sep 10, 2002
Capping layer
ADVANCED MICRO DEVICES INC6 citations74
US6337246B1Jan 8, 2002
Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing
ADVANCED MICRO DEVICES INC13 citations73
US6268624B1Jul 31, 2001
Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing
ADVANCED MICRO DEVICES INC11 citations73
US6787840B1Sep 7, 2004
Nitridated tunnel oxide barriers for flash memory technology circuitry
ADVANCED MICRO DEVICES INC5 citations63
US6635943B1Oct 21, 2003
Method and system for reducing charge gain and charge loss in interlayer dielectric formation
ADVANCED MICRO DEVICES INC3 citations63
US6589841B1Jul 8, 2003
Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate
ADVANCED MICRO DEVICES INC3 citations63
US6548334B1Apr 15, 2003
Capping layer
ADVANCED MICRO DEVICES INC5 citations63
US6399984B1Jun 4, 2002
Species implantation for minimizing interface defect density in flash memory devices
ADVANCED MICRO DEVICES INC4 citations63
US6342415B1Jan 29, 2002
Method and system for providing reduced-sized contacts in a semiconductor device
ADVANCED MICRO DEVICES INC0 citations52
US6284600B1Sep 4, 2001
Species implantation for minimizing interface defect density in flash memory devices
ADVANCED MICRO DEVICES INC0 citations52
US6093650AJul 25, 2000
Method for fully planarized conductive line for a stack gate
ADVANCED MICRO DEVICES INC1 citations42
SANDISK CORP
3 patentsUS7592225B2Sep 22, 2009
Methods of forming spacer patterns using assist layer for high density semiconductor devices
SANDISK CORP13 citations84
US7960266B2Jun 14, 2011
Spacer patterns using assist layer for high density semiconductor devices
SANDISK CORP3 citations63
US7773403B2Aug 10, 2010
Spacer patterns using assist layer for high density semiconductor devices
SANDISK CORP2 citations63