Inventor

EGBERT CHANDAN

US32 patents

⚠️ This page may combine multiple inventors who share the name “EGBERT CHANDAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EGBERT CHANDAN

ADVANCED MICRO DEVICES INC

Layer 3 switching logic architecture in an integrated network switch

Queuing structure and method for prioritization of frames in a network switch

Method and apparatus for selectively discarding packets for blocked output queues in the network switch

Packet classification using hash key signatures generated from interrupted hash function

Method and network switch having dual forwarding models with a virtual lan overlay

Method and apparatus for managing learning in an address table in memory

Method and apparatus for capturing source and destination traffic

Method and apparatus for reclaiming buffers

Method and apparatus for resetting, enabling and freezing a communication device in a diagnostic process

Method and apparatus for transmitting multiple copies by replicating data identifiers

Methods and apparatus for preventing under-flow conditions in a multiple-port switching device

Network switch port configured for generating an index key for a network switch routing table using a programmable hash function

Apparatus and method in a network switch for swapping memory access slots between gigabit port and expansion port

Method and apparatus for controlling initiation of transmission of data as a function of received data

External rules checker interface

Arrangement in a network switch for prioritizing data frames based on user-defined frame attributes

Apparatus and method for programmable memory access slot assignment

Arrangement for switching data packets in a network switch based on subnet identifier

Arrangement for reducing layer 3 header data supplied to switching logic on a network switch

Multiple key lookup arrangement for a shared switching logic address table in a network switch

Multiport switch with plurality of logic engines for simultaneously processing different respective data frames

Apparatus and method in a network switch for dynamically assigning memory interface slots between gigabit port and expansion port

Arrangement for programming selected device registers during initialization from an external memory

Method and apparatus for managing bin chains in a memory

Apparatus and method for disabling external frame forwarding device for use with a network switch

In-band management of a stacked group of switches by a single CPU

INTEL CORP

Concept for approximate deduplication in storage and memory

Reservation architecture for overcommitted memory

Reservation architecture for overcommitted memory

Memory pressure notifier

Hardware-assisted paging mechanisms

Lazy memory deduplication