Inventor

SUN SHIH-WEI

TW71 patents

⚠️ This page may combine multiple inventors who share the name “SUN SHIH-WEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SUN SHIH-WEI

UNITED MICROELECTRONICS CORP

Method of gap filling

Silicon on insulator (SOI) dram cell structure and process

Dual damascene process

Planarization technique for DRAM cell capacitor electrode

Multi-step high density plasma chemical vapor deposition process

Method for forming an interconnect structure with air gap compatible with unlanded vias

Interconnect structure with air gap compatible with unlanded vias

Interconnect structure with gas dielectric compatible with unlanded vias

Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit

Method of fabricating a shallow-trench isolation structure in integrated circuit

Method for growing hemispherical grain silicon

High density plasma chemical vapor deposition process

Process and structure for embedded DRAM

Method of manufacturing multi-layer metal capacitor

Multi-layer metal capacitor

Method of fabricating dual gate structure of embedded DRAM

Method of fabricating DRAM

Method of fabricating a dynamic random access memory device

Fabricating method of a barrier layer

Method for forming self-aligned contact window

Metal-oxide semiconductor field effect transistor device fabrication process

Method of Making High-K Dielectrics for embedded DRAMS

Differential gate oxide thickness by nitrogen implantation for mixed mode and embedded VLSI circuits

Active layer mask with dummy pattern

SRAM having improved soft-error immunity

Method of forming a self-aligned silicide device

Method of making a self-aligned silicide component

Intermetal dielectric layer formation with low dielectric constant using high density plasma chemical vapor deposition process

Method of planarizing an inter-layer dielectric layer

Method for increasing capacitance

Method of forming bonding pad

Method of fabricating embedded DRAM

MOTOROLA INC

Protection device for an intergrated circuit and method of formation

Fabrication of mixed thin-film and bulk semiconductor substrate for integrated circuit applications

Structure for shielding conductors

Process for forming a structure which electrically shields conductors

Method for locos isolation using a framed oxidation mask and a polysilicon buffer layer

Thin film silicon on insulator semiconductor integrated circuit with electrostatic damage protection and method

Process for forming semiconductor-on-insulator device

Process for fabricating a semiconductor device including a nonvolatile memory cell

Process for forming a semiconductor device having a metal-semiconductor compound

Method of forming dual field oxide isolation

Process for forming a feature on a substrate without recessing the surface of the substrate

Semiconductor device with ESD protection

Process for forming a semiconductor device with ESD protection

Process for fabricating a graded-channel MOS device

(unassigned)

Manufacturing method for self-aligned local interconnects and contacts simultaneously

Method for unlanded via etching using etch stop

UNITED MICROELECTRICS CORP

Fabrication of buried channel devices with shallow junction depth

LIU CHIH-CHIEN

High density plasma chemical vapor deposition process