Inventor

CHOW LAP-WAI

US63 patents

⚠️ This page may combine multiple inventors who share the name “CHOW LAP-WAI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHOW LAP-WAI

HRL LAB LLC

CMOS-compatible MEM switches and method of making

Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact

CMOS-compatible MEM switches and method of making

Method and apparatus using silicide layer for protecting integrated circuits from reverse engineering

Memory with a bit line block and/or a word line block for preventing reverse engineering

Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact

Integrated circuit with reverse engineering protection

Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the same

Implanted hidden interconnections in a semiconductor device for preventing reverse engineering

Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations

Integrated circuit structure with programmable connector/isolator

Memory with a bit line block and/or a word line block for preventing reverse engineering

Use of silicon block process step to camouflage a false transistor

Symmetric non-intrusive and covert technique to render a transistor permanently non-operable

Cryptographic CPU architecture with random instruction masking to thwart differential power analysis

Covert transformation of transistor properties as a circuit protection method

Implanted hidden interconnections in a semiconductor device for preventing reverse engineering

Symmetric non-intrusive and covert technique to render a transistor permanently non-operable

Conductive channel pseudo block process and circuit to inhibit reverse engineering

Covert transformation of transistor properties as a circuit protection method

Integrated circuit modification using well implants

Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide

HUGHES ELECTRONICS CORP

Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering

Secure integrated circuit

Integrated circuit security system and method with implanted interconnections

Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering

Camouflaged circuit structure with step implants

Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering

Process for fabricating secure integrated circuit

Method and apparatus for selectively performing a plurality of logic operations and memory functions

RAYTHEON CO

Split sense amplifier and staging buffer for wide memory architecture

Integrated circuit with reverse engineering protection

Conductive channel pseudo block process and circuit to inhibit reverse engineering

Use of silicon block process step to camouflage a false transistor

Wide memory architecture vector processor using nxP bits wide memory bus for transferring P n-bit vector operands in one cycle

SHU DAVID B

Cryptographic architecture with instruction masking and other techniques for thwarting differential power analysis

Cryptographic bus architecture for the prevention of differential power analysis

Cryptographic architecture with random instruction masking to thwart differential power analysis

RAMBUS INC

Always-on FinFET with camouflaged punch stop implants for protecting integrated circuits from reverse engineering

Electrically isolated gate contact in FINFET technology for camouflaging integrated circuits from reverse engineering

Physically unclonable camouflage structure and methods for fabricating same

COCCHI RONALD P

Building block for a secure CMOS logic cell library

Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processing

SYPHERMEDIA INT INC

Physically unclonable camouflage structure and methods for fabricating same

Physically unclonable camouflage structure and methods for fabricating same

CHOW LAP WAI

Camouflaging a standard cell based integrated circuit

PROMTEK

Multilayered integrated circuit with extraneous conductive traces

HUGHES AIRCRAFT CO

High speed, low power pipelined logic circuit

CLARK JR WILLIAM M

Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer

INSIDE SECURE

Method and apparatus for camouflaging an integrated circuit using virtual camouflage cells