Inventor

WOHL PETER

US31 patents

⚠️ This page may combine multiple inventors who share the name “WOHL PETER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WOHL PETER

SYNOPSYS INC

Deterministic BIST architecture tolerant of uncertain scan chain outputs

Efficient compression and application of deterministic patterns in a logic BIST architecture

Method and system for controlling test data volume in deterministic test pattern generation

Deterministic bist architecture including MISR filter

System and method for time slicing deterministic patterns for reseeding in logic built-in self-test

System and process of extracting gate-level descriptions from simulation tables for formal verification

Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit

Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation

System and method for automatic generation of gate-level descriptions from table-based descriptions for electronic design automation

Fully X-tolerant, very high scan compression scan test systems and techniques

Fully X-tolerant, very high scan compression scan test systems and techniques

Increasing scan compression by using X-chains

Scan compression circuit and method of design therefor

Launch-on-shift support for on-chip-clocking

Reducing X-masking effect for linear time compactors

Two-level compression through selective reseeding

Method and system for generating an ATPG model of a memory from behavioral descriptions

Multi-cycle test generation and source-based simulation

Multiple clock and clock cycle selection for x-tolerant logic built in self test (XLBIST)

Per-shift X-tolerant logic built-in self-test

Increasing PRPG-based compression by delayed justification

Diagnosis and debug with truncated simulation

Diagnosis and debug using truncated simulation

Distributed test pattern generation and synchronization

Increasing compression by reducing padding patterns

IBM

Integrated circuit clocking technique and circuit therefor

Hierarchical fault modeling system and method

Integrated circuit chip and pass gate logic family therefor

WOHL PETER

Increasing PRPG-based compression by delayed justification

Fully X-tolerant, very high scan compression scan test systems and techniques

ATPG and compression by using majority gates