Inventor

WAICUKAUSKI JOHN A

US25 patents

⚠️ This page may combine multiple inventors who share the name “WAICUKAUSKI JOHN A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WAICUKAUSKI JOHN A

SYNOPSYS INC

Deterministic BIST architecture tolerant of uncertain scan chain outputs

Efficient compression and application of deterministic patterns in a logic BIST architecture

Deterministic bist architecture including MISR filter

System and method for time slicing deterministic patterns for reseeding in logic built-in self-test

Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit

Fully X-tolerant, very high scan compression scan test systems and techniques

Fully X-tolerant, very high scan compression scan test systems and techniques

Increasing scan compression by using X-chains

Scan compression circuit and method of design therefor

Launch-on-shift support for on-chip-clocking

Reducing X-masking effect for linear time compactors

Two-level compression through selective reseeding

Multi-cycle test generation and source-based simulation

Per-shift X-tolerant logic built-in self-test

Increasing PRPG-based compression by delayed justification

Diagnosis and debug with truncated simulation

Diagnosis and debug using truncated simulation

IBM

Weighted random pattern testing apparatus and method

Hybrid pattern self-testing of integrated circuits

Weighted random pattern testing apparatus and method

Weighted random pattern testing apparatus and method

Weighted random pattern testing apparatus and method

WOHL PETER

Increasing PRPG-based compression by delayed justification

Fully X-tolerant, very high scan compression scan test systems and techniques

ATPG and compression by using majority gates