Inventor

SODANI AVINASH

US75 patents

⚠️ This page may combine multiple inventors who share the name “SODANI AVINASH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SODANI AVINASH

MARVELL ASIA PTE LTD

Architecture to support color scheme-based synchronization for machine learning

Architecture to support tanh and sigmoid operations for inference acceleration in machine learning

System and method to manage power throttling

Method and apparatus for performing machine learning operations in parallel on machine learning hardware

System and method for hardware-based register protection mechanism

System and method to manage power to a desired power profile

Architecture to support synchronization between core and inference engine for machine learning

Data transmission between memory and on chip memory of inference engine for machine learning via a single data gathering instruction

Instruction set architecture (ISA) format for multiple instruction set architectures in machine learning inference engine

Method and apparatus for performing machine learning operations in parallel on machine learning hardware

Architecture to support tanh and sigmoid operations for inference acceleration in machine learning

System and method for INT9 quantization

Address interleaving for machine learning

System and method for INT9 quantization

Architecture for table-based mathematical operations for inference acceleration in machine learning

Architecture for table-based mathematical operations for inference acceleration in machine learning

Address interleaving for machine learning

Architecture to support color scheme-based synchronization for machine learning

System and method to manage power throttling

System and method to manage power to a desired power profile

System and methods for tag-based synchronization of tasks for machine learning operations

Architecture to support synchronization between core and inference engine for machine learning

Power management and transitioning cores within a multicore system from idle mode to operational mode over a period of time

Architecture to support synchronization between core and inference engine for machine learning

Power management and current/ramp detection mechanism

Power management and current/ramp detection mechanism

INTEL CORP

Method and apparatus for rescheduling operations in a processor

Register alias table cache to map a logical register to a physical register

Tracking an oldest processor event using information stored in a register and queue entry

Thermal throttling of electronic devices

Flow optimization and prediction for VSSE memory operations

Method and system for transforming memory location references in instructions

Method and apparatus for user-level thread synchronization with a monitor and MWAIT architecture

Minimizing snoop traffic locally and across cores on a chip multi-core fabric

Method and apparatus for limiting ports in a register alias table having high-bandwidth and low-bandwidth structures

Providing multiple memory modes for a processor including internal memory

CAVIUM LLC

Streaming engine for machine learning architecture

Architecture for dense operations in machine learning inference engine

Array-based inference engine for machine learning

Architecture of crossbar of inference engine

Single instruction set architecture (ISA) format for multiple ISAS in machine learning inference engine

Systems and methods for programmable hardware architecture for machine learning

Architecture for irregular operations in machine learning inference engine

HINTON GLENN J

Controlling non-redundant execution in a redundant multithreading (RMT) processor

Obtaining data for redundant multithreading (RMT) execution

MARVELL ASIA PTE LTD REGISTRATION NO 199702379M

System and methods for tag-based synchronization of tasks for machine learning operations

Power management and transitioning cores within a multicore system from idle mode to operational mode over a period of time

WISCONSIN ALUMNI RES FOUND

Computer with dynamic instruction reuse

MARVELL INT LTD

Data transmission between memory and on chip memory of inference engine for machine learning via a single data gathering instruction

MARDEN MORRIS

Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor