Inventor

HAN JIN-PING

US69 patents

⚠️ This page may combine multiple inventors who share the name “HAN JIN-PING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAN JIN-PING

IBM

Pulse shaping unit cell and array for symmetric updating

BEOL cross-bar array ferroelectric synapse units for domain wall movement

Indirect readout FET

Threshold voltage improvement employing fluorine implantation and adjustment oxide layer

Multi-terminal cross-point synaptic device using nanocrystal dot structures

Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end

Mobile ferroelectric single domain wall implementation of a symmetric resistive processing unit

Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end

Semiconductor device including optimized gate stack profile

Multi-layer phase change memory device

One-transistor synapse cell with weight adjustment

One-transistor synapse cell with weight adjustment

Gap fill of metal stack in replacement gate process

Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS back-end

BEOL cross-bar array ferroelectric synapse units for domain wall movement

Mobile ferroelectric single domain wall implementation of a symmetric resistive processing unit

Phase change multilayer heterostructure with multiple heaters

Magnetic tunnel junction device

Memory cell with a variable element and a phase change memory

Proximity heater to lower RRAM forming voltage

Phase change memory cell with double active volume

Media capture device with power saving and encryption features for partitioned neural network

Multi-layer phase change memory device

Racetrack synapse for neuromorphic applications

Semiconductor devices and methods of manufacture thereof

Heater for phase change material memory cell

Embedded heater in a phase change memory material

Analog circuit for softmax function

Phase change memory with graded heater

Indirect readout FET

Symmetrically programmable resistive synapse for RPU using current-programmed single domain wall ferroelectric

Image sensor with analog sample and hold circuit control for analog neural networks

INFINEON TECHNOLOGIES AG

Methods of manufacturing semiconductor devices and structures thereof

Strained semiconductor device and method of making same

Semiconductor devices and methods of manufacturing thereof

Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same

Method for forming isolation structures

Semiconductor devices having recesses filled with semiconductor materials

Device performance improvement using flowfill as material for isolation structures

Methods of manufacturing resistors and structures thereof

CMOS devices having stress-altering material lining the isolation trenches and methods of manufacturing thereof

STAHRENBERG KNUT

Methods of fabricating semiconductor devices and structures thereof

Methods of manufacturing resistors and structures thereof

SAMSUNG ELECTRONICS CO LTD

Stress optimization in dual embedded epitaxially grown semiconductor processing

Metallic synapses for neuromorphic and evolvable hardware

HAN JIN-PING

Semiconductor devices and methods of manufacture thereof

Semiconductor devices and methods of manufacturing thereof

UNIV YALE

Ferroelectric dynamic random access memory

YANG JONG HO

Methods of forming p-channel field effect transistors having SiGe source/drain regions

ELLER MANFRED

Semiconductor devices and methods of manufacture thereof