Inventor

OH HYUNG-ROK

KR60 patents

⚠️ This page may combine multiple inventors who share the name “OH HYUNG-ROK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OH HYUNG-ROK

SAMSUNG ELECTRONICS CO LTD

Variable resistance memory device and method of manufacturing the same

Layout structure in semiconductor memory device comprising global work lines, local work lines, global bit lines and local bit lines

Semiconductor memory device and method for reducing cell activation during write operations

Semiconductor memory device and method for biasing dummy line therefor

Semiconductor memory device capable of compensating for leakage current

Data read circuit for use in a semiconductor memory and a memory thereof

Writing driver circuit of phase-change memory

Phase random access memory with high density

Programming method of controlling the amount of write current applied to phase change memory device and write driver circuit therefor

Semiconductor memory device having resistive memory cells and method of testing the same

Circuits and methods for adaptive write bias driving of resistive non-volatile memory devices

Resistance random access memory having common source line

Nonvolatile memory devices that utilize read/write merge circuits

Memory system, memory device and apparatus including writing driver circuit for a variable resistive memory

Phase change random access memory

Magneto-resistive RAM having multi-bit cell array structure

Phase-change semiconductor memory device and method of programming the same

Semiconductor memory device

Phase change memory device providing compensation for leakage current

Phase-change memory device and method that maintains the resistance of a phase-change material in a reset state within a constant resistance range

Write driver circuit for controlling a write current applied to a phase change memory based on an ambient temperature

Phase-changeable memory device and read method thereof

One-time programmable devices including chalcogenide material and electronic systems including the same

Nonvolatile memory device using resistance material

Bi-directional resistive random access memory capable of multi-decoding and method of writing data thereto

Nonvolatile memory device having memory and reference cells

Memory cell of a resistive semiconductor memory device, a resistive semiconductor memory device having a three-dimensional stack structure, and related methods

Phase change random access memory

Nonvolatile memory devices having multi-filament variable resistivity memory cells therein

Nonvolatile memory devices having enhanced bit line and/or word line driving capability

Writing driver circuit of phase-change memory

Magnetic memory device implementing read operation tolerant to bitline clamp voltage (VREF)

Method of testing PRAM device

Data read circuit for use in a semiconductor memory and a method therefor

Layout structure in semiconductor memory device comprising global word lines, local word lines, global bit lines and local bit lines

Phase change random access memory device

Method of testing PRAM device

Resistance semiconductor memory device having three-dimensional stack and word line decoding method thereof

Nonvolatile memory device having twin memory cells

Non-volatile memory including sub cell array and method of writing data thereto

Phase change random access memory device

Memory system including a resistance variable memory device

Phase change memory device and associated wordline driving circuit

Semiconductor memory device

Phase change random access memory, boosting charge pump and method of generating write driving voltage

KIM CHAN-KYUNG

Nonvolatile memory device with a clamping voltage generation circuit for compensating the variations in memory cell parameters

Data read circuit, a non-volatile memory device having the same, and a method of reading data from the non-volatile memory device

OH HYUNG-ROK

Stacked MRAM device and memory system having the same

Multi-layer semiconductor memory device comprising error checking and correction (ECC) engine and related ECC method

LEE YUN-SANG

Semiconductor memory devices for alternately selecting bit lines