Inventor

HADY FRANK T

US41 patents

⚠️ This page may combine multiple inventors who share the name “HADY FRANK T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HADY FRANK T

INTEL CORP

Method of implementing off-chip cache memory in dual-use SRAM memory for network processors

Heterogeneous processors sharing a common cache

Apparatus, method and system for counting logic events, determining logic event histograms and for identifying a logic event in a logic environment

Method and apparatus for generating a frequency distribution representation using integrated counter-based instrumentation

Apparatus, method and system for determining application runtimes based on histogram or distribution information

Multi-level memory with direct access

Managing disturbance induced errors

Caching for heterogeneous processors

Caching bypass

System for dynamically configuring system logic device coupled to the microprocessor to optimize application performance by reading from selection table located in non-volatile memory

System and method for automatic and adaptive use of active network performance measurement techniques to find the fastest source

Method and apparatus for processing sequential writes to a block group of physical blocks in a memory device

Managing disturbance induced errors

Apparatus, method and system for counting logic events, determining logic event histograms and for identifying a logic event in a logic environment

Caching for heterogeneous processors

Caching for heterogeneous processors

Load reduced nonvolatile memory interface

Load reduced nonvolatile memory interface

Coherent multiprocessing enabled compute in storage and memory

Multi-level memory with direct access

Multi-level memory with direct access

Caching for heterogeneous processors

Caching for heterogeneous processors

Matching memory transactions to cache line boundaries

Method and apparatus for gathering queue performance data

Multi-level memory with direct access

Managing disturbance induced errors

Method and apparatus for processing sequential writes to portions of an addressable unit

Coordinating operations of network and host processors

Method and apparatus for connecting an additional processor to a bus with symmetric arbitration

Method and system for simultaneously displaying the throughput on multiple busses

Providing aggregated directory structure

HADY FRANK T

Heterogeneous processors sharing a common cache

Caching for heterogeneous processors

Powering on devices via intermediate computing device

MOONEY STEPHEN R

Interchangeable power and signal contacts for IO connectors

Universal IO connector and interface capable of both wired and wireless operation

FANNING BLAISE

Multi-level memory with direct access

TRIKA SANJEEV N

Method and system to perform caching based on file-level heuristics

SK HYNIX NAND PRODUCT SOLUTIONS CORP

Load reduced nonvolatile memory interface

JAUSSI JAMES E

Host controlled IO power management