Inventor

BUETI SERAFINO

US20 patents

⚠️ This page may combine multiple inventors who share the name “BUETI SERAFINO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BUETI SERAFINO

IBM

Design structures, method and systems of powering on integrated circuit

Dynamic critical path detector for digital logic circuit paths

Design structures of powering on integrated circuit

Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design

Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design

Apparatus and method for implementing an integrated circuit IP core library architecture

Structure for hardware assisted bus state transition circuit using content addressable memories

Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees

Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees

Structure for task based debugger (transaction-event-job-trigger)

Task based debugger (transaction-event-job-trigger)

Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry

Method and apparatus for monitoring integrated circuit temperature through deterministic path delays

Communication systems and methods using microelectronics power distribution network

Method and systems of powering on integrated circuit

System and method for system-on-chip interconnect verification

System and method for system-on-chip interconnect verification

BUETI SERAFINO

Dynamic critical path detector for digital logic circuit paths

On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variations

BERGKVIST JR JOHN JOSEPH

Simulation of digital circuits