Inventor

HO WILLIAM WAI YAN

US39 patents

⚠️ This page may combine multiple inventors who share the name “HO WILLIAM WAI YAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HO WILLIAM WAI YAN

WORLDWIDE PRO LTD

Barycenter compact model to determine IR drop exact solution for circuit network

Solving a hierarchical circuit network using a barycenter compact model

Partitioning electronic circuits for simulation on multicore processors

Network tearing for circuit simulation

Using a Barycenter compact model for a circuit network

Partitioning a system graph for circuit simulation to obtain an exact solution

Using a Barycenter compact model for a circuit network

Partitioning electronic circuits for simulation on multiple processors

Hierarchical visualization-based analysis of integrated circuits

Hierarchical visualization-based analysis of integrated circuits

Solving a circuit network in hierarchical, multicore, and distributed computing environment

Validating integrated circuit simulation results

Solving a circuit network in multicore or distributed computing environment

Validating integrated circuit simulation results

Partitioning electronic circuits for simulation on multicore processors

Validating integrated circuit simulation results

Determining IR drops for circuit networks using Barycenter model

Using barycenter compact model to determine IR drop for circuit network

Using a barycenter compact model for a circuit network

Hierarchical 3D structure generation and intelligent compaction method using barycenter compaction model

HO WILLIAM WAI YAN

Simulating circuits by distributed computing

Solving a hierarchical circuit network using a Barycenter compact model

Hierarchical visualization-based analysis of integrated circuits

Using multiple processors to simulate electronic circuits

Simulating circuits using network tearing

Solving a circuit network in hierarchical, multicore, and distributed computing environment

Validating very large network simulation results

Validating integrated circuit simulation results

Network tearing for circuit simulation

Validating circuit simulation results

SYNOPSYS INC

Connectivity-based approach for extracting layout parasitics

Layer-based rule checking for an integrated circuit layout

Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach

Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach

Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach

Connectivity-based approach for extracting layout parasitics

PACK ROBERT C

Modeling and simulating the impact of imperfectly patterned via arrays on integrated circuits

Hierarchical variation analysis of integrated circuits

EPIC DESIGN TECHNOLOGY INC

Connectivity-based approach for extracting parasitic layout in an integrated circuit