Inventor

SHIU SHINYE

US29 patents

⚠️ This page may combine multiple inventors who share the name “SHIU SHINYE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHIU SHINYE

APPLE INC

Mechanism for sharing private caches in a SoC

System cache with partial write valid states

System cache with speculative read engine

System cache with fine grain power management

System cache with sticky removal engine

Cache allocation scheme optimized for browsing applications

Memory power savings in idle display case

Integrated circuit with multiported memory supercell and data path switching circuitry

Advanced coarse-grained cache power management

Memory power savings in idle display case

Coherence processing with pre-kill mechanism to avoid duplicated transaction identifiers

System cache with coarse grain power management

Advanced fine-grained cache power management

Scheme to escalate requests with address conflicts

Processor to memory with coherency bypass

GOOGLE INC

Hardware-assisted memory compression management using page filter and system MMU

Method and apparatus for monitoring system performance and dynamically updating memory sub-system settings using software to optimize performance and power consumption

Methods and systems for memory de-duplication

Transparent hardware-assisted memory decompression

Memory system architecture

SHIU SHINYE

Dynamic leakage control for memory arrays

Dynamic level shifter for interfacing signals referenced to different power supply domains

Memory having asynchronous read with fast read output

BISWAS SUKALPA

System cache with sticky allocation

System cache with cache hint control

System cache with quota-based control

GOOGLE LLC

Integrated DRAM with low-voltage swing I/O

Transparent hardware-assisted memory decompression

BURNETTE JAMES E

Dynamic level shifter circuit and ring oscillator using the same