Inventor

MULA LIRON

IL64 patents

⚠️ This page may combine multiple inventors who share the name “MULA LIRON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MULA LIRON

MELLANOX TECHNOLOGIES LTD

TDMA networking using commodity NIC/switch

Packet scheduling system with desired physical transmission time for packets

Network adapter with time-aware packet-processing pipeline

Physical hardware clock chaining

Methods and systems for error-correction decoding

Template-based packet parsing

Hardware clock with built-in accuracy check

Packet switches

Receive-side timestamp accuracy

Multihost clock synchronization

Probabilistic normalized congestion indication based on packet size

Offloading node CPU in distributed redundant storage systems

Efficient parsing tuned to prevalent packet types

Physical layer synchronization

Reducing retransmission latency

Bi-directional encryption/decryption device for underlay and overlay operations

Global policers

Head-of-queue blocking for multiple lossless queues

Template-based packet parsing

Bi-directional encryption/decryption device for underlay and overlay operations

System to trigger time-dependent action

Redundancy data bus inversion sharing

Electro-optical interconnect assembly with integral tampering protection

Controller which adjusts clock frequency based on received symbol rate

End-to-end flow control with intermediate media access control security devices

Cardinality-based traffic control

Adaptive port routing

Power-optimized and shared buffer

Co-packaged switch with integrated quantum key distribution capabilities

MELLANOX TECH TLV LTD

Using consistent hashing for ECMP routing

Head-of-queue blocking for multiple lossless queues

Network switch operating as packet generator

Direct memory access (DMA) engine for diagnostic data

Global policers

Efficient memory utilization and egress queue fairness

Listing congestion notification packet generation by switch

Reusing switch ports for external buffer network

Deduplication of mirror traffic in analyzer aggregation network

Power-efficient activation of multi-lane ports in a network element

Using consistent hashing for ECMP routing

Rate limiting in a multi-chassis environment by exchanging information between peer network elements

Estimating multiple distinct-flow counts in parallel

Telemetry event aggregation

Switch with controlled queuing for multi-host endpoints

Switch arbitration based on distinct-flow counts

Time division communication via optical switch fabric

Adaptive flow prioritization

Zero-copy buffering of traffic of long-haul links

Packet-content based WRED protection

NVIDIA CORP

Hardware latency monitoring for memory device input/output requests