Inventor

SEREBRIN BENJAMIN C

US57 patents

⚠️ This page may combine multiple inventors who share the name “SEREBRIN BENJAMIN C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SEREBRIN BENJAMIN C

SEREBRIN BENJAMIN C

Memory structure to store interrupt state for inactive guests

Minivisor entry point in virtual machine monitor address space

Interrupt virtualization

Hardware interrupt arbitration in virtualized computer systems

Guest interrupt manager that records interrupts for guests and delivers interrupts to executing guests

Virtual address mapping using rule based aliasing to achieve fine grained page translation

Redirection table and predictor for fetching instruction routines in a virtual machine guest

Monitoring interrupt acceptances in guests

Translate and verify instruction for a processor

World switch between virtual machines with selective storage of state information

Processor and method configured to determine an exit mechanism using an intercept configuration for a virtual machine

Methods, apparatus, and articles of manufacture to virtualize performance counters

Increasing granularity of dirty bit information in hardware assisted memory management systems

Separate page table base address for minivisor

Atomic program verification

Programmable atomic memory using stored atomic procedures

Caching binary translations for virtual machine guest

Programmable atomic memory using hardware validation agent

GOOGLE INC

Address validation using signatures

Computer interconnect isolation

Counting events using hardware performance counters and annotated instructions

Computer interconnect isolation

Address caching in switches

Virtual machine systems

Byte application migration

Counting events using hardware performance counters and annotated instructions

User mode interrupts

Thread waiting in a multithreaded processor architecture

Address caching in switches

GOOGLE LLC

Address validation using signatures

Address validation using signatures

Computer interconnect isolation

Data caching

Address validation using signatures

Address validation using signatures

Address validation using signatures

Computer interconnect isolation

Address validation using signatures

VMWARE INC

Increasing granularity of dirty bit information in hardware assisted memory management systems

Latency reduction for direct memory access operations involving address translation

Increasing granularity of dirty bit information

Increasing granularity of dirty bit information in hardware assisted memory management systems

ADVANCED MICRO DEVICES INC

Guest interrupt controllers for each processor to aid interrupt virtualization

Synchronization of processor time stamp counters to master counter

Interrupt virtualization

GLOBALFOUNDRIES INC

Placing virtual machine monitor (VMM) code in guest context to speed memory mapped input/output virtualization

Fast, automatically scaled processor time stamp counter

Execute-only memory and mechanism enabling execution from execute-only memory for minivisor

WOLLER THOMAS R

Hypervisor isolation of processor cores to enable computing accelerator cores

MEHTA BHAVESH

System and method for supporting finer-grained copy-on-write page sizes