Inventor

SADOVNIKOV ALEXEI

US67 patents

⚠️ This page may combine multiple inventors who share the name “SADOVNIKOV ALEXEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SADOVNIKOV ALEXEI

TEXAS INSTRUMENTS INC

Sinker to buried layer connection region for narrow deep trenches

Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect

Dual deep trenches for high voltage isolation

Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect

Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS technologies

BICMOS device having commonly defined gate shield in an ED-CMOS transistor and base in a bipolar transistor

Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS technologies

Semiconductor device with deep trench isolation and trench capacitor

Method of improving lateral BJT characteristics in BCD technology

Semiconductor device with deep trench isolation and trench capacitor

Split-gate lateral extended drain MOS transistor structure and process

MOS transistor with folded channel and folded drift region

Low dynamic resistance low capacitance diodes

Drain extended transistor

DMOS transistor having thick gate oxide and STI and method of fabricating

Carbon, nitrogen and/or fluorine co-implants for low resistance transistors

Transistor having an emitter region with a silicide spaced apart from a base contact

Bipolar junction transistor with constricted collector region having high gain and early voltage product

Bipolar junction transistor with constricted collector region having high gain and early voltage product

Fabricating transistors with implanting dopants at first and second dosages in the collector region to form the base region

DMOS transistor having thick gate oxide and STI and method of fabricating

Integrated circuit with resurf region biasing under buried insulator layers

Corrugated metal oxide semiconductor transistor

Vertical deep trench and deep trench island based deep n-type well diode and diode triggered protection device

False collectors and guard rings for semiconductor devices

Vertical deep trench and deep trench island based deep n-type well diode and diode triggered protection device

MOS transistor with folded channel and folded drift region

LDMOS with high-k drain STI dielectric

Semiconductor doped region with biased isolated members

Semiconductor doped region with biased isolated members

Sinker to buried layer connection region for narrow deep trenches

Rugged LDMOS with field plate

Integrated JFET structure with implanted backgate

Breakdown diodes and methods of making the same

Integrated circuit with resurf region biasing under buried insulator layers

Dual deep trenches for high voltage isolation

Integrated circuit with resurf region biasing under buried insulator layers

NAT SEMICONDUCTOR CORP

Method of reducing fringing capacitance in a MOSFET

Method of etching a lateral trench under an extrinsic base and improved bipolar transistor

Method of forming a self-aligned bipolar transistor structure using a selectively grown emitter

Polysilicon-edge, base-emitter super self-aligned, low-power, high-frequency bipolar transistor and method of forming the transistor

Single poly bipolar transistor and method that uses a selectively epitaxially grown highly-boron-doped silicon layer as a diffusion source for an extrinsic base region

Polysilicon-edge, low-power, high-frequency bipolar transistor and method of forming the transistor

Low doped base spacer for reduction of emitter-base capacitance in bipolar transistors with selectively grown epitaxial base

Polysilicon-edge, low-power, high-frequency bipolar transistor and method of forming the transistor

Method of controlling the breakdown voltage of BSCRs and BJT clamps

Bipolar transistor with a box-type germanium profile that lies outside of the emitter-base depletion region

EL-DIWANY MONIR

Self-aligned bipolar transistor structure

FOOTE RICHARD W

Method for manufacturing bipolar transistors

BABCOCK JEFFREY A

Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structures