Inventor

KELLER IGOR

US43 patents

⚠️ This page may combine multiple inventors who share the name “KELLER IGOR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KELLER IGOR

CADENCE DESIGN SYSTEMS INC

System, method and computer program product for handling small aggressors in signal integrity analysis

Timing and signal integrity analysis of integrated circuits with semiconductor process variations

Robust calculation of crosstalk delay change in integrated circuit design

Method and system for crosstalk analysis

Characterizing electronic component parameters including on-chip variations and moments

Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stages

Static timing analysis methods for integrated circuit designs using a multi-CCC current source model

Methods and apparatus for waveform based variational static timing analysis

Method and system or generating a current source model of a gate

Methods, systems, and articles of manufacture for enhancing timing analyses with reduced timing libraries for electronic designs

View data sharing for efficient multi-mode multi-corner timing analysis

Method and apparatus for comprehension of common path pessimism during timing model extraction

Method and apparatus for yield calculation using statistical timing data that accounts for path and stage delay correlation

Delay propagation for multiple logic cells using correlation and coskewness of delays and slew rates in an integrated circuit design

Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact

Generating an equivalent waveform model in static timing analysis

Systems and methods for statistical static timing analysis

Systems and methods for statistical static timing analysis

Lumped aggressor model for signal integrity timing analysis

Constructing equivalent waveform models for static timing analysis of integrated circuit designs

System and method for accurate modeling of back-miller effect in timing analysis of digital circuits

Analyzing clock jitter using delay calculation engine

Using waveform propagation for accurate delay calculation

Methods, systems, and computer program product for characterizing an electronic design with a susceptibility window

Pseudo-inverter configuration for signal electromigration analysis

Receiver dependent selection of a worst-case timing event for static timing analysis

Methods, systems, and computer program product for characterizing timing behavior of an electronic design with a derived current waveform

Cell instance charge model for delay calculation

Method, system, and product for deferred merge based method for graph based analysis pessimism reduction

Efficient delay calculations in replicated designs

Circuit design modification using timing-based yield calculation

KELLER IGOR

Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs

Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs

Compact modeling of circuit stages for static timing analysis of integrated circuit designs

Equivalent waveform model for static timing analysis of integrated circuit designs

Methods for compact modeling of circuit stages for static timing analysis of integrated circuit designs

KARIAT VINOD

Sensitivity and static timing analysis for integrated circuit designs using a multi-CCC current source model

Methods, systems, and apparatus for timing and signal integrity analysis of integrated circuits with semiconductor process variations

Method and apparatus for thermal analysis

Multi-CCC current source models and static timing analysis methods for integrated circuit designs

TIWARY SAURABH K

Methods and apparatus for waveform based variational static timing analysis

Methods and apparatus for waveform based variational static timing analysis

Waveform based variational static timing analysis