Inventor
ONISHI SHOHJI
JP5 patents
Patents
5 patentsUS6175535B1Jan 16, 2001
Cycle control circuit for extending a cycle period of a dynamic memory device subarray
IBM28 citations91
US7113443B2Sep 26, 2006
Method of address distribution time reduction for high speed memory macro
IBM6 citations62
US6172920B1Jan 9, 2001
Data transfer using two-stage bit switch in memory circuit
IBM3 citations61
US7187614B2Mar 6, 2007
Array read access control using MUX select signal gating of the read port
IBM0 citations46
US7230873B2Jun 12, 2007
Forced pulldown of array read bitlines for generating MUX select signals
IBM0 citations43