Inventor
BACHAND DEREK T
US24 patents
⚠️ This page may combine multiple inventors who share the name “BACHAND DEREK T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
23 patentsUS6499090B1Dec 24, 2002
Prioritized bus request scheduling mechanism for processing devices
INTEL CORP80 citations99
US7487305B2Feb 3, 2009
Prioritized bus request scheduling mechanism for processing devices
INTEL CORP50 citations96
US6782457B2Aug 24, 2004
Prioritized bus request scheduling mechanism for processing devices
INTEL CORP33 citations96
US6606692B2Aug 12, 2003
Prioritized bus request scheduling mechanism for processing devices
INTEL CORP29 citations96
US6732242B2May 4, 2004
External bus transaction scheduling system
INTEL CORP63 citations95
US6668309B2Dec 23, 2003
Snoop blocking for cache coherency
INTEL CORP48 citations95
US6321297B1Nov 20, 2001
Avoiding tag compares during writes in multi-level cache hierarchy
INTEL CORP80 citations94
US6578116B2Jun 10, 2003
Snoop blocking for cache coherency
INTEL CORP18 citations92
US6216208B1Apr 10, 2001
Prefetch queue responsive to read request sequences
INTEL CORP39 citations92
US6078981AJun 20, 2000
Transaction stall technique to prevent livelock in multiple-processor systems
INTEL CORP33 citations92
US6434677B1Aug 13, 2002
Method and apparatus for altering data length to zero to maintain cache coherency
INTEL CORP15 citations91
US7133981B2Nov 7, 2006
Prioritized bus request scheduling mechanism for processing devices
INTEL CORP8 citations74
US7143242B2Nov 28, 2006
Dynamic priority external transaction system
INTEL CORP8 citations73
US6654837B1Nov 25, 2003
Dynamic priority external transaction system
INTEL CORP10 citations73
US6460119B1Oct 1, 2002
Snoop blocking for cache coherency
INTEL CORP11 citations73
US6401172B1Jun 4, 2002
Recycle mechanism for a processing agent
INTEL CORP6 citations73
US6209068B1Mar 27, 2001
Read line buffer and signaling protocol for processor
INTEL CORP12 citations73
US6735675B2May 11, 2004
Method and apparatus for altering data length to zero to maintain cache coherency
INTEL CORP10 citations72
US6578114B2Jun 10, 2003
Method and apparatus for altering data length to zero to maintain cache coherency
INTEL CORP9 citations72
US6412091B2Jun 25, 2002
Error correction system in a processing agent having minimal delay
INTEL CORP3 citations62
US6269465B1Jul 31, 2001
Error correction system in a processing agent having minimal delay
INTEL CORP2 citations62
US10133670B2Nov 20, 2018
Low overhead hierarchical connectivity of cache coherent agents to a coherent fabric
INTEL CORP0 citations51
US7555603B1Jun 30, 2009
Transaction manager and cache for processing agent
INTEL CORP1 citations51