Inventor

TAN JUAN BOON

SG150 patents

⚠️ This page may combine multiple inventors who share the name “TAN JUAN BOON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAN JUAN BOON

GLOBALFOUNDRIES SG PTE LTD

Magnetic shielding of MRAM package

Integrated circuit with memory cells having reliable interconnection

High-Density STT-MRAM with 3D arrays of MTJs in multiple levels of interconnects and method for producing the same

Integrated two-terminal device and logic device with compact interconnects having shallow via for embedded application

Integrated magnetic random access memory with logic device

STT-MRAM flip-chip magnetic shielding and method for producing the same

Robust chamfer design for seal ring

Top electrode dome formation

Semiconductor chips with seal rings and electronic test structures, semiconductor wafers including the semiconductor chips, and methods for fabricating the same

Integrated inductor and magnetic random access memory device

Integrated circuits having crack-stop structures and methods for fabricating the same

Integrated magnetic random access memory with logic device

Magnetic shielding for MTJ device or bit

Integrated magnetic random access memory with logic device having low-k interconnects

Methods for fabricatingintegrated circuits with spin torque transfer magnetic randomaccess memory (STT-MRAM) including a passivation layer formed along lateral sidewalls of a magnetic tunnel junction of the STT-MRAM

Bond pad reliability of semiconductor devices

Integrated circuit system employing low-k dielectrics and method of manufacture thereof

Programmable interposer using RRAM platform

Memory devices and methods of forming the same

MTJ bottom metal via in a memory cell and method for producing the same

Memory devices and methods of forming the same

MRAM chip magnetic shielding

Embedded MRAM in interconnects and method for producing the same

MRAM device with improved seal ring and method for producing the same

Magnetic shielding of STT-MRAM in multichip packaging and method of manufacturing the same

Integrated circuits including a dummy metal feature and methods of forming the same

Interposers for integrated circuits with multiple-time programming and methods for manufacturing the same

Magnetic tunnel junction stack alignment scheme

Planar passivation for pads

Integrated circuit structures with spin torque transfer magnetic random access memory ultilizing aluminum metallization layers and methods for fabricating the same

Through via contacts with insulated substrate

Magnetic memory device and method of forming thereof

Non-volatile memory elements with a narrowed electrode

Integrated two-terminal device with logic device for embedded application

Device without zero mark layer

Pillar contact extension and method for producing the same

Integrated magnetic random access memory with logic device having low-K interconnects

Integrated two-terminal device with logic device for embedded application

Integrated circuits with optical modulators and photodetectors and methods for producing the same

Non-volatile memory device with TSI/TSV application

Resistive memory device and methods of making such a resistive memory device

MRAM magnetic shielding with fan-out wafer level packaging

CHARTERED SEMICONDUCTOR MFG

Alignment mark strategy for oxide CMP

Intermetal dielectric layer for integrated circuits

Printing optimized global alignment mark at contact/via layers

Alignment mark strategy for oxide CMP

Reliable interconnects

LU YUE KANG

TSV backside processing using copper damascene interconnect technology

TAN JUAN BOON

Back-side MOM/MIM devices

GLOBALFOUNDRIES US INC

Conductive structures for contacting a top electrode of an embedded memory device and methods of making such contact structures on an IC product