Inventor
FANG LI-CHIH
TW16 patents
⚠️ This page may combine multiple inventors who share the name “FANG LI-CHIH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
POWERTECH TECHNOLOGY INC
15 patentsUS7619305B2Nov 17, 2009
Semiconductor package-on-package (POP) device avoiding crack at solder joints of micro contacts during package stacking
POWERTECH TECHNOLOGY INC31 citations88
US9761568B2Sep 12, 2017
Thin fan-out multi-chip stacked packages and the method for manufacturing the same
POWERTECH TECHNOLOGY INC12 citations83
US10593629B2Mar 17, 2020
Semiconductor package with a conductive casing for heat dissipation and electromagnetic interference (EMI) shield and manufacturing method thereof
POWERTECH TECHNOLOGY INC9 citations82
US9831219B2Nov 28, 2017
Manufacturing method of package structure
POWERTECH TECHNOLOGY INC6 citations82
US7927919B1Apr 19, 2011
Semiconductor packaging method to save interposer
POWERTECH TECHNOLOGY INC11 citations79
US9659911B1May 23, 2017
Package structure and manufacturing method thereof
POWERTECH TECHNOLOGY INC3 citations72
US10607860B2Mar 31, 2020
Package structure and chip structure
POWERTECH TECHNOLOGY INC2 citations71
US10431549B2Oct 1, 2019
Semiconductor package and manufacturing method thereof
POWERTECH TECHNOLOGY INC2 citations71
US10276510B2Apr 30, 2019
Manufacturing method of package structure having conductive shield
POWERTECH TECHNOLOGY INC4 citations71
US9825010B2Nov 21, 2017
Stacked chip package structure and manufacturing method thereof
POWERTECH TECHNOLOGY INC4 citations71
US10840200B2Nov 17, 2020
Manufacturing method of chip package structure comprising encapsulant having concave surface
POWERTECH TECHNOLOGY INC1 citations62
US7691676B1Apr 6, 2010
Mold array process for semiconductor packages
POWERTECH TECHNOLOGY INC3 citations61
US10163834B2Dec 25, 2018
Chip package structure comprising encapsulant having concave surface
POWERTECH TECHNOLOGY INC0 citations52
US10950557B2Mar 16, 2021
Stacked chip package structure and manufacturing method thereof
POWERTECH TECHNOLOGY INC0 citations50
US9972554B2May 15, 2018
Wafer level chip scale package having continuous through hole via configuration and fabrication method thereof
POWERTECH TECHNOLOGY INC0 citations37