Inventor

LUEH GUEI-YUAN

US127 patents

⚠️ This page may combine multiple inventors who share the name “LUEH GUEI-YUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LUEH GUEI-YUAN

INTEL CORP

Static compilation of instrumentation code for debugging support

Method of run-time tracking of object references in Java programs

Method of run-time tracking of object references in Java programs

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

Debugging support using dynamic re-compilation

Method for eliminating common subexpressions from java byte codes

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

Systems and methods for affine-partitioning programs onto multiple processing units

Method for fast exception handling

Method and apparatus for reducing the overhead of virtual method invocations

Generating efficient parallel code using partitioning, coalescing, and degenerative loop and guard removal

Apparatus and methods for restoring synchronization to object-oriented software applications in managed runtime environments

Inlining with stack trace cache-based dynamic profiling

Method and system of controlling dynamically compiled native code size

Software scoreboard information and synchronization

Splitting the computation space to optimize parallel code

Method for fast translation of java byte codes into efficient native processor code

Systems and methods for performing nibble-sized operations on matrix elements

Graphics processing unit processing and caching improvements

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

Hierarchical general register file (GRF) for execution block

Efficient preemption for graphics processors

Methods and apparatus for optimizing the operating speed and size of a computer program

Method and apparatus for improving the performance of garbage collection using stack trace cache

Method for implementing dynamic type checking

Method and system of permitting stack allocation to programs having open-world features

Compressing data in a cache memory

Dynamic division optimization for a just-in-time compiler

Bank assignment for partitioned register banks

Mechanism to store reordered data with compression

Inter-procedural allocation of stacked registers for a processor

Method for providing garbage collection support

Method and apparatus for maintaining exception reporting for register promotion

Engine to enable high speed context switching via on-die storage

Hierarchical general register file (GRF) for execution block

Thread prefetch mechanism

Engine to enable high speed context switching via on-die storage

Thread priority mechanism

Page faulting and selective preemption

Techniques for graphics data prefetching

Method and apparatus for efficient execution of nested branches on a graphics processor unit

Instruction prefetch mechanism

Instruction prefetch mechanism

Method and apparatus for performing reduction operations on a plurality of associated data element values

WANG PERRY

Programming environment for heterogeneous processor resource integration

KOKER ALTUG

Engine to enable high speed context switching via on-die storage

LIAO SHIH-WEI

Compiler-based scheduling optimization hints for user-level threads

GEORGE BIJU

Register liveness analysis for SIMD architectures