P

Inventor

EVANS MATTHEW LUCIEN

GB36 patents

Patents

36 patents
US11467960B1Oct 11, 2022

Access frequency caching hardware structure

ADVANCED RISC MACH LTD15 citations85
US9378162B2Jun 28, 2016

Handling and routing interrupts to virtual processors

ADVANCED RISC MACH LTD18 citations80
US11068268B2Jul 20, 2021

Data structure processing

ADVANCED RISC MACH LTD2 citations73
US10838877B2Nov 17, 2020

Protected exception handling

ADVANCED RISC MACH LTD3 citations73
US10558590B2Feb 11, 2020

Secure initialisation

ADVANCED RISC MACH LTD3 citations73
US10324858B2Jun 18, 2019

Access control

ADVANCED RISC MACH LTD3 citations73
US11449437B2Sep 20, 2022

Invalidation of a target realm in a realm hierarchy

ADVANCED RISC MACH LTD2 citations71
US11176061B2Nov 16, 2021

Realm identifiers for realms for memory access control

ADVANCED RISC MACH LTD2 citations71
US11113209B2Sep 7, 2021

Realm identifier comparison for translation cache lookup

ADVANCED RISC MACH LTD2 citations71
US9697136B2Jul 4, 2017

Descriptor ring management

ADVANCED RISC MACH LTD3 citations70
US9218302B2Dec 22, 2015

Page table management

ADVANCED RISC MACH LTD2 citations63
US12066953B2Aug 20, 2024

Handling address translation requests

ADVANCED RISC MACH LTD0 citations62
US11334499B2May 17, 2022

Method for locating metadata

ADVANCED RISC MACH LTD0 citations62
US11269634B2Mar 8, 2022

Data structure relinquishing

ADVANCED RISC MACH LTD0 citations62
US11119943B2Sep 14, 2021

Handling address translation requests

ADVANCED RISC MACH LTD0 citations62
US11194485B2Dec 7, 2021

Realm execution context masking and saving

ADVANCED RISC MACH LTD1 citations60
US11494092B2Nov 8, 2022

Address space access control

ADVANCED RISC MACH LTD0 citations56
US11144458B2Oct 12, 2021

Apparatus and method for performing cache maintenance over a virtual page

ADVANCED RISC MACH LTD0 citations52
US12197916B2Jan 14, 2025

Processing instructions selected from a first instruction set in a first processing mode and instructions selected from a second different instruction set in a second processing mode

ADVANCED RISC MACH LTD0 citations51
US11550620B2Jan 10, 2023

Task dispatch

ADVANCED RISC MACH LTD0 citations51
US11009841B2May 18, 2021

Initialising control data for a device

ADVANCED RISC MACH LTD0 citations51
US12386755B2Aug 12, 2025

Data processing apparatus and method for address translation

ADVANCED RISC MACH LTD0 citations50
US11874778B2Jan 16, 2024

Realm management unit-private memory regions

ADVANCED RISC MACH LTD0 citations50
US11816227B2Nov 14, 2023

Interrupting export of memory regions

ADVANCED RISC MACH LTD0 citations50
US11461248B2Oct 4, 2022

Code realms

ADVANCED RISC MACH LTD0 citations50
US11347660B2May 31, 2022

Sub-realms

ADVANCED RISC MACH LTD0 citations50
US11294676B2Apr 5, 2022

Exception return instruction variants for realm-based switching

ADVANCED RISC MACH LTD0 citations50
US11237957B2Feb 1, 2022

Scrub-commit state for memory region

ADVANCED RISC MACH LTD0 citations50
US11086659B2Aug 10, 2021

Masking of architectural state associated with a realm

ADVANCED RISC MACH LTD0 citations50
US11016910B2May 25, 2021

Memory region locking using lock/unlock flag state for exclusive rights to control memory access

ADVANCED RISC MACH LTD0 citations50
US10423537B2Sep 24, 2019

Address space resizing table for simulation of processing of target program code on a target data processing apparatus

ADVANCED RISC MACH LTD0 citations50
US12547523B2Feb 10, 2026

Page access frequency tracking

ADVANCED RISC MACH LTD0 citations49
US10146602B2Dec 4, 2018

Termination of stalled transactions relating to devices overseen by a guest system in a host-guest virtualized system

ADVANCED RISC MACH LTD0 citations41
US8924615B2Dec 30, 2014

Communication of message signalled interrupts

ADVANCED RISC MACH LTD0 citations41
US9507728B2Nov 29, 2016

Bridge circuitry for translating between memory transactions of first type and memory transactions of a second type

ADVANCED RISC MACH LTD0 citations40
US10102139B2Oct 16, 2018

Memory management for address translation including detecting and handling a translation error condition

ADVANCED RISC MACH LTD0 citations31