Inventor

IZENBERG EREZ

IL94 patents

⚠️ This page may combine multiple inventors who share the name “IZENBERG EREZ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IZENBERG EREZ

AMAZON TECH INC

Flexible remote direct memory access

Time synchronization with distributed grand master

Time synchronization monitoring with client mirroring

Network congestion detection and resolution

Configurable logic platform

Hardware security accelerator

Packet processing cache

FPGA-enabled compute instances

Flexible remote direct memory access

Flexible remote direct memory access

Configurable logic platform with multiple reconfigurable regions

Hardware security accelerator

Configurable logic platform with multiple reconfigurable regions

Configurable logic platform

Flexible remote direct memory access

Generic data integrity check

Configurable parser and a method for parsing information units

Controlling access to previously-stored logic in a reconfigurable logic device

Generic data integrity check

Configurable logic platform with multiple reconfigurable regions

Controlling shared resources and context data

Universal offloading engine

Generating transactions with a configurable port

Configurable parser and a method for parsing information units

Dynamically configurable pipeline

Non-coherent and coherent connections in a multi-chip system

Configurable logic platform

Transaction based remote direct memory access

Configurable parser and a method for parsing information units

Configurable logic platform

Low-latency packet processing for network device

Configurable parser and a method for parsing information units

Controlling access to previously-stored logic in a reconfigurable logic device

Hybrid remote direct memory access

Intermediate host integrated circuit between virtual machine instance and customer programmable logic

Hardware security accelerator

Low latency interrupt with existence of interrupt moderation

Hybrid remote direct memory access

Network traffic load balancing using rotating hash

MARVELL ISRAEL MISL LTD

Apparatus and a method for allocating upstream bandwidth of a shared upstream channel of an optical network

Combined hardware/software forwarding mechanism and method

Efficient packet classification in a network device

Versatile optical network interface methods and systems

IZENBERG EREZ

Deficit round robin scheduling using multiplication factors

Combined hardware/software forwarding mechanism and method

ANNAPURNA LABS LTD

Hybrid remote direct memory access

Configurable parser and a method for parsing information units

BEN-MAYOR SHAUL

Enhanced parsing and classification in a packet processor

AMIT EREZ

Dual clock first-in first-out (FIFO) memory system

BENHAIM GUY M

Apparatus and a method for allocating upstream bandwidth of a shared upstream channel of an optical network