Inventor
CUTTER DANIEL
US26 patents
⚠️ This page may combine multiple inventors who share the name “CUTTER DANIEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
25 patentsUS6728845B2Apr 27, 2004
SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues
INTEL CORP119 citations98
US6694380B1Feb 17, 2004
Mapping requests from a processing unit that uses memory-mapped input-output space
INTEL CORP227 citations98
US6681300B2Jan 20, 2004
Read lock miss control and queue management
INTEL CORP89 citations98
US6671827B2Dec 30, 2003
Journaling for parallel hardware threads in multithreaded processor
INTEL CORP75 citations98
US6427196B1Jul 30, 2002
SRAM controller for parallel processor architecture including address and command queue and arbiter
INTEL CORP152 citations98
US6324624B1Nov 27, 2001
Read lock miss control and queue management
INTEL CORP88 citations98
US6631462B1Oct 7, 2003
Memory shared between processing threads
INTEL CORP74 citations96
US10270464B1Apr 23, 2019
Method and apparatus for high performance compression and decompression
INTEL CORP17 citations94
US7305500B2Dec 4, 2007
Sram controller for parallel processor architecture including a read queue and an order queue for handling requests
INTEL CORP31 citations92
US8020142B2Sep 13, 2011
Hardware accelerator
INTEL CORP21 citations91
US7607068B2Oct 20, 2009
Apparatus and method for generating a Galois-field syndrome
INTEL CORP9 citations83
US11095305B1Aug 17, 2021
Method and apparatus for high performance compression and decompression
INTEL CORP2 citations73
US10528539B2Jan 7, 2020
Optimized selection of hash collision chains
INTEL CORP5 citations73
US10691529B2Jun 23, 2020
Supporting random access of compressed data
INTEL CORP5 citations72
US12021551B2Jun 25, 2024
Method and apparatus for efficient deflate decompression using content-addressable data structures
INTEL CORP0 citations62
US11243836B2Feb 8, 2022
Supporting random access of compressed data
INTEL CORP0 citations62
US9128818B2Sep 8, 2015
Memory mapping in a processor having multiple programmable units
INTEL CORP1 citations62
US7912886B2Mar 22, 2011
Configurable exponent FIFO
INTEL CORP2 citations62
US12074618B2Aug 27, 2024
Flexible compression header and code generation
INTEL CORP0 citations52
US9830285B2Nov 28, 2017
Memory mapping in a processor having multiple programmable units
INTEL CORP0 citations52
US9830284B2Nov 28, 2017
Memory mapping in a processor having multiple programmable units
INTEL CORP0 citations52
US9824038B2Nov 21, 2017
Memory mapping in a processor having multiple programmable units
INTEL CORP0 citations52
US9824037B2Nov 21, 2017
Memory mapping in a processor having multiple programmable units
INTEL CORP0 citations52
US11955995B2Apr 9, 2024
Apparatus and method for two-stage lossless data compression, and two-stage lossless data decompression
INTEL CORP0 citations50
US7730356B2Jun 1, 2010
Method and apparatus for testing mathematical algorithms
INTEL CORP0 citations50