Inventor

AMIRINENI SUNDEEP

US40 patents

Patents

40 patents

US10445638B1Oct 15, 2019

Configurable function approximation based on hardware selection of mapping table content

AMAZON TECH INC1 citations63

US12468507B1Nov 11, 2025

Reducing power consumption in integrated circuits

AMAZON TECH INC0 citations62

US12198041B2Jan 14, 2025

Efficient utilization of processing element array

AMAZON TECH INC0 citations62

US11294599B1Apr 5, 2022

Registers for restricted memory

AMAZON TECH INC0 citations62

US10943167B1Mar 9, 2021

Restructuring a multi-dimensional array

AMAZON TECH INC1 citations62

US11775430B1Oct 3, 2023

Memory access for multiple circuit components

AMAZON TECH INC0 citations60

US11507378B1Nov 22, 2022

Hardware engine with configurable instructions

AMAZON TECH INC0 citations59

US12271732B1Apr 8, 2025

Configuration of a deep vector engine using an opcode table, control table, and datapath table

AMAZON TECH INC0 citations52

US12333274B2Jun 17, 2025

Data-type-aware clock-gating

AMAZON TECH INC0 citations50

US12182691B1Dec 31, 2024

Increasing performance of computational array accelerators

AMAZON TECH INC0 citations50

US10990408B1Apr 27, 2021

Place and route aware data pipelining

AMAZON TECH INC0 citations50

US12346643B1Jul 1, 2025

Testing integrated circuit designs with accelerated replay

AMAZON TECH INC0 citations46

US10877552B1Dec 29, 2020

Dynamic power reduction through data transfer request limiting

AMAZON TECH INC0 citations40

AMIRINENI SUNDEEP

Patents

Restructuring a multi-dimensional array

Accelerated quantized multiply-and-add operations

Multiple accumulate busses in a systolic array

Debug for computation networks using error detection codes

Reducing dynamic power consumption in arrays

Registers for restricted memory

Adaptive timeout mechanism

Memory access for multiple circuit components

Hardware implementation of mathematical functions

Weight loading in an array

Parallelism within a systolic array using multiple accumulate busses

Isolating unresponsive customer logic from a bus

Filtering control plane decision requests for forwarding network packets

Configurable function approximation based on switching mapping table content

Parametric mathematical function approximation in integrated circuits

Adaptive timeout mechanism

Accelerated quantized multiply-and-add operations

Hardware engine with configurable instructions

Data selection circuit

Multiple accumulate busses in a systolic array

Efficient utilization of processing element array

Multiple accumulate busses in a systolic array

Fine-grained access memory controller

Resizable scratchpad memory

Hardware implementation of mathematical functions

Throughput increase for compute engine

Configurable vector compute engine

Configurable function approximation based on hardware selection of mapping table content

Reducing power consumption in integrated circuits

Efficient utilization of processing element array

Registers for restricted memory

Restructuring a multi-dimensional array

Memory access for multiple circuit components

Hardware engine with configurable instructions

Configuration of a deep vector engine using an opcode table, control table, and datapath table

Data-type-aware clock-gating

Increasing performance of computational array accelerators

Place and route aware data pipelining

Testing integrated circuit designs with accelerated replay

Dynamic power reduction through data transfer request limiting