Inventor
CUSHING DAVID E
18 patents
⚠️ This page may combine multiple inventors who share the name “CUSHING DAVID E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HONEYWELL INF SYSTEMS
14 patentsUS4161784AJul 17, 1979
Microprogrammable floating point arithmetic unit capable of performing arithmetic operations on long and short operands
HONEYWELL INF SYSTEMS249 citations98
US4438493AMar 20, 1984
Multiwork memory data storage and addressing technique and apparatus
HONEYWELL INF SYSTEMS43 citations92
US4323967AApr 6, 1982
Local bus interface for controlling information transfers between units in a central subsystem
HONEYWELL INF SYSTEMS45 citations92
US4460959AJul 17, 1984
Logic control system including cache memory for CPU-memory transfers
HONEYWELL INF SYSTEMS9 citations74
US4455606AJun 19, 1984
Logic control system for efficient memory to CPU transfers
HONEYWELL INF SYSTEMS14 citations74
US4451883AMay 29, 1984
Bus sourcing and shifter control of a central processing unit
HONEYWELL INF SYSTEMS13 citations74
US4360869ANov 23, 1982
Control store organization for a data processing system
HONEYWELL INF SYSTEMS13 citations73
US4348724ASep 7, 1982
Address pairing apparatus for a control store of a data processing system
HONEYWELL INF SYSTEMS9 citations73
US4130879ADec 19, 1978
Apparatus for performing floating point arithmetic operations using submultiple storage
HONEYWELL INF SYSTEMS11 citations73
US4295202AOct 13, 1981
Hexadecimal digit shifter output control by a programmable read only memory
HONEYWELL INF SYSTEMS8 citations66
US4467417AAug 21, 1984
Flexible logic transfer and instruction decoding system
HONEYWELL INF SYSTEMS2 citations63
US4467416AAug 21, 1984
Logic transfer and decoding system
HONEYWELL INF SYSTEMS3 citations63
US4349874ASep 14, 1982
Buffer system for supply procedure words to a central processor unit
HONEYWELL INF SYSTEMS5 citations63
US4348723ASep 7, 1982
Control store test selection logic for a data processing system
HONEYWELL INF SYSTEMS3 citations63
BULL HN INFORMATION SYST
4 patentsUS5003204AMar 26, 1991
Edge triggered D-type flip-flop scan latch cell with recirculation capability
BULL HN INFORMATION SYST110 citations94
US4980819ADec 25, 1990
Mechanism for automatically updating multiple unit register file memories in successive cycles for a pipelined processing system
BULL HN INFORMATION SYST30 citations92
US5134706AJul 28, 1992
Bus interface interrupt apparatus
BULL HN INFORMATION SYST26 citations91
US4933909AJun 12, 1990
Dual read/write register file memory
BULL HN INFORMATION SYST36 citations88