Inventor
MADHYASTHA SADHANA
US5 patents
Patents
5 patentsUS6631093B2Oct 7, 2003
Low power precharge scheme for memory bit lines
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US6914848B2Jul 5, 2005
Word line transistor stacking for leakage control
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US6629194B2Sep 30, 2003
Method and apparatus for low power memory bit line precharge
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US6628539B2Sep 30, 2003
Multi-entry register cell
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US6341099B1Jan 22, 2002
Reducing power consumption in a data storage device
INTEL CORP0 citations49