Inventor

HARTLEY RICHARD I

US31 patents

Patents

31 patents

US5559334ASep 24, 1996

Epipolar reconstruction of 3D structures

GEN ELECTRIC60 citations96

US5187754AFeb 16, 1993

Forming, with the aid of an overview image, a composite image from a mosaic of images

GEN ELECTRIC309 citations96

US4985834AJan 15, 1991

System and method employing pipelined parallel circuit architecture for displaying surface structures of the interior region of a solid body

GEN ELECTRIC101 citations96

US5175843ADec 29, 1992

Computer-aided design method for restructuring computational networks to minimize shimming delays

GEN ELECTRIC58 citations95

US5325198AJun 28, 1994

Unitary transform methods of identifying defects in imaging devices

GEN ELECTRIC64 citations94

US5544254AAug 6, 1996

Classifying and sorting crystalline objects

GEN ELECTRIC115 citations93

US5317755AMay 31, 1994

Systolic array processors for reducing under-utilization of original design parallel-bit processors with digit-serial processors by using maximum common divisor of latency around the loop connection

GEN ELECTRIC22 citations93

US5396531AMar 7, 1995

Method of achieving reduced dose X-ray fluoroscopy by employing statistical estimation of poisson noise

GEN ELECTRIC46 citations92

US5293415AMar 8, 1994

X-ray fluoroscopy system for reducing dosage employing iterative power ratio estimation

GEN ELECTRIC35 citations92

US5159598AOct 27, 1992

Buffer integrated circuit providing testing interface

GEN ELECTRIC30 citations92

US4939687AJul 3, 1990

Serial-parallel multipliers using serial as well as parallel addition of partial products

GEN ELECTRIC24 citations92

US5361307ANov 1, 1994

Correlation methods of identifying defects in imaging devices

GEN ELECTRIC35 citations91

US5177691AJan 5, 1993

Measuring velocity of a target by Doppler shift, using improvements in calculating discrete Fourier transform

GEN ELECTRIC40 citations91

US5550376AAug 27, 1996

Method of achieving reduced dose X-ray fluoroscopy by employing transform-based estimation of Poisson noise

GEN ELECTRIC13 citations74

US5084834AJan 28, 1992

Digit-serial linear combining apparatus

GEN ELECTRIC9 citations74

US5034908AJul 23, 1991

Digit-serial transversal filters

GEN ELECTRIC11 citations74

US5025257AJun 18, 1991

Increased performance of digital integrated circuits by processing with multiple-bit-width digits

GEN ELECTRIC11 citations74

US5016011AMay 14, 1991

Increased performance of digital integrated circuits by processing with multiple-bit-width digits

GEN ELECTRIC15 citations74

US5010511AApr 23, 1991

Digit-serial linear combining apparatus useful in dividers

GEN ELECTRIC18 citations74

US4972358ANov 20, 1990

Computation of discrete fourier transform using recursive techniques

GEN ELECTRIC13 citations74

US4951221AAug 21, 1990

Cell stack for variable digit width serial architecture

GEN ELECTRIC18 citations74

US4910700AMar 20, 1990

Bit-sliced digit-serial multiplier

GEN ELECTRIC15 citations74

US4860240AAug 22, 1989

Low-latency two's complement bit-serial multiplier

GEN ELECTRIC19 citations74

US5115437AMay 19, 1992

Internal test circuitry for integrated circuits using token passing to select testing ports

GEN ELECTRIC11 citations73

US5119378AJun 2, 1992

Testing of integrated circuits including internal test circuitry and using token passing to select testing ports

GEN ELECTRIC9 citations72

US5034909AJul 23, 1991

Digit-serial recursive filters

GEN ELECTRIC5 citations63

US4942396AJul 17, 1990

To-digit-serial converters for systems processing data in digit-serial format

GEN ELECTRIC4 citations63

US4905175AFeb 27, 1990

Digit-serial shifters constructed from basic cells

GEN ELECTRIC6 citations63

HARTLEY RICHARD I

Patents

Epipolar reconstruction of 3D structures

Forming, with the aid of an overview image, a composite image from a mosaic of images

System and method employing pipelined parallel circuit architecture for displaying surface structures of the interior region of a solid body

Computer-aided design method for restructuring computational networks to minimize shimming delays

Unitary transform methods of identifying defects in imaging devices

Classifying and sorting crystalline objects

Systolic array processors for reducing under-utilization of original design parallel-bit processors with digit-serial processors by using maximum common divisor of latency around the loop connection

Method of achieving reduced dose X-ray fluoroscopy by employing statistical estimation of poisson noise

X-ray fluoroscopy system for reducing dosage employing iterative power ratio estimation

Buffer integrated circuit providing testing interface

Serial-parallel multipliers using serial as well as parallel addition of partial products

Correlation methods of identifying defects in imaging devices

Measuring velocity of a target by Doppler shift, using improvements in calculating discrete Fourier transform

Method of calibration of imaging devices

Array multiplier adapted for tiled layout by silicon compiler

Data format converters for use with digit-serial signals

Method of achieving reduced dose X-ray fluoroscopy by employing transform-based estimation of Poisson noise

Digit-serial linear combining apparatus

Digit-serial transversal filters

Increased performance of digital integrated circuits by processing with multiple-bit-width digits

Increased performance of digital integrated circuits by processing with multiple-bit-width digits

Digit-serial linear combining apparatus useful in dividers

Computation of discrete fourier transform using recursive techniques

Cell stack for variable digit width serial architecture

Bit-sliced digit-serial multiplier

Low-latency two&#39;s complement bit-serial multiplier

Internal test circuitry for integrated circuits using token passing to select testing ports

Testing of integrated circuits including internal test circuitry and using token passing to select testing ports

Digit-serial recursive filters

To-digit-serial converters for systems processing data in digit-serial format

Digit-serial shifters constructed from basic cells

Low-latency two's complement bit-serial multiplier